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cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 revision: v1.71 date: april 11, 2017
rev. 1.71 2 april 11, 2017 rev. 1.71 3 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom table of contents eates cpu features ......................................................................................................................... 6 periphera l features ................................................................................................................. 6 general description ......................................................................................... 7 selection table ................................................................................................. 7 block diagram .................................................................................................. 8 pin assignment ........... ..................................................................................... 8 pin description .......... .................................................................................... 10 absolute maximum ratings .......................................................................... 14 d.c. characteristics ....................................................................................... 15 a.c. characteristics ....................................................................................... 16 adc electrical characteristics ... .................................................................. 17 opa electrical characteristics ..................................................................... 17 lvr electrical characteristics ...................................................................... 18 lcd electrical characteristics C ht66f004 ................................................ 18 power on reset electrical characteristics .................................................. 18 system architecture ...................................................................................... 19 clocking and pipelining ......................................................................................................... 19 program counter ................................................................................................................... 20 stack ..................................................................................................................................... 21 arithmetic and logic unit C alu ........................................................................................... 21 flash program memory ................................................................................. 22 structure ................................................................................................................................ 22 special vectors ..................................................................................................................... 22 look-up table ............. ........................................................................................................... 22 table program example ........................................................................................................ 23 in circuit programming C icp ............................................................................................... 24 on-chip debug support C ocds ......................................................................................... 24 ram data memory ......................................................................................... 25 structure ................................................................................................................................ 25 general purpose data memory ............................................................................................ 25 special purpose data memory ............................................................................................. 25 special function register description ........................................................ 29 indirect addressing registers C iar0, iar1 ......................................................................... 29 memory pointers C mp0, mp1 .............................................................................................. 29 bank pointer C bp ................................................................................................................. 30 accumulator C acc ............................................................................................................... 30 program counter low register C pcl .................................................................................. 30 look-up table registers C tblp, tblh ................................................................................ 30 status register C status .................................................................................................... 31
rev. 1.71 2 april 11, 2017 rev. 1.71 3 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom eeprom data memory ........... ....................................................................... 32 eeprom data memory structure ........................................................................................ 32 eeprom registers ............ .................................................................................................. 33 reading data from the eeprom ........................................................................................ 34 writing data to the eeprom ................................................................................................ 35 write protection ..................................................................................................................... 35 eeprom interrupt ............. ................................................................................................... 35 programming considerations ............. ................................................................................... 36 oscillator ........................................................................................................ 37 oscillator overview ............. .................................................................................................. 37 system clock confgurations ................................................................................................ 37 internal rc oscillator C hirc ............. .................................................................................. 38 internal 32khz oscillator C lirc ........................................................................................... 38 supplementary oscillator ...................................................................................................... 38 operating modes and system clocks ......................................................... 38 system clocks ...................................................................................................................... 38 system operation modes ...................................................................................................... 39 control register .................................................................................................................... 40 operating mode switching .................................................................................................... 42 normal mode to slow mode switching ........................................................................... 43 slow mode to normal mode switching .......................................................................... 44 entering the sleep0 mode .................................................................................................. 44 entering the sleep1 mode .................................................................................................. 45 entering the idle0 mode ...................................................................................................... 45 entering the idle1 mode ...................................................................................................... 45 standby current considerations ........................................................................................... 46 wake-up ................................................................................................................................ 46 watchdog timer ........... .................................................................................. 47 watchdog timer clock source .............................................................................................. 47 watchdog timer control register ............. ............................................................................ 47 watchdog timer operation ................................................................................................... 48 reset and initialisation .................................................................................. 49 reset functions ............. ....................................................................................................... 50 reset initial conditions ......................................................................................................... 53 input/output ports ......................................................................................... 56 pull-high resistors ................................................................................................................ 57 port a wake-up ............. ........................................................................................................ 58 i/o port control registers ..................................................................................................... 58 pin-shared functions ............. ............................................................................................... 59 i/o pin structures .................................................................................................................. 64 system clock output pin clo ............................................................................................... 65 programming considerations ............. ................................................................................... 65
rev. 1.71 4 april 11, 2017 rev. 1.71 5 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom timer modules C tm .......... ............................................................................ 66 introduction ........................................................................................................................... 66 tm operation ............. ........................................................................................................... 66 tm clock source ............. ...................................................................................................... 66 tm interrupts ......................................................................................................................... 67 tm external pins ................................................................................................................... 67 tm input/output pin control register ................................................................................... 67 programming considerations ............. ................................................................................... 68 standard type tm C stm .......... .................................................................... 69 standard tm operation ............. ............................................................................................ 69 standard type tm register description ............................................................................... 70 standard type tm operating modes .................................................................................... 74 compare output mode ............. ............................................................................................. 74 timer/counter mode ............................................................................................................. 77 pwm output mode ............. ................................................................................................... 77 single pulse mode ................................................................................................................ 80 capture input mode .............................................................................................................. 82 periodic type tm C ptm ................................................................................ 83 periodic tm operation ............. ............................................................................................. 83 periodic type tm register description ................................................................................. 84 periodic type tm operating modes ...................................................................................... 88 compare match output mode ............................................................................................... 88 timer/counter mode ............................................................................................................. 91 pwm output mode ............. ................................................................................................... 91 single pulse output mode .................................................................................................... 93 capture input mode .............................................................................................................. 95 analog to digital converter .......... ................................................................ 97 a/d overview ............. ........................................................................................................... 97 a/d converter register description ...................................................................................... 98 a/d converter data registers C sadol, sadoh ............. ................................................... 98 a/d converter control registers C sadc0, sadc1, sadc 2, pasr, pbsr ....................... 99 a/d operation ..................................................................................................................... 101 a/d converter input signal ................................................................................................. 102 conversion rate and timing diagram ................................................................................ 103 summary of a/d conversion steps ............. ........................................................................ 104 programming considerations ............. ................................................................................. 105 a/d transfer function ............. ............................................................................................ 105 a/d programming example s ............................................................................................... 106
rev. 1.71 4 april 11, 2017 rev. 1.71 5 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom interrupts ...................................................................................................... 108 interrupt registers ............................................................................................................... 108 interrupt operation ............................................................................................................... 114 external interrupt ............. ..................................................................................................... 116 multi-function interrupt ......................................................................................................... 116 a/d converter interrupt ........................................................................................................ 116 time base interrupts ............................................................................................................ 117 eeprom interrupt ............. .................................................................................................. 118 tm interrupts ........................................................................................................................ 118 interrupt wake-up function .................................................................................................. 118 programming considerations ............. .................................................................................. 118 scom function for lcd C ht66f004 .......................................................... 119 lcd peration ........................................................................................................................ 119 lcd bias current control ................................................................................................... 120 application circuits ........... .......................................................................... 121 instruction set .............................................................................................. 122 introduction ......................................................................................................................... 122 instruction timing ................................................................................................................ 122 moving and transferring data ............................................................................................. 122 arithmetic operations .......................................................................................................... 122 logical and rotate operation ............................................................................................. 123 branches and control transfer ........................................................................................... 123 bit operations ..................................................................................................................... 123 table read operations ....................................................................................................... 123 other operations ............. .................................................................................................... 123 instruction set summary .......... .................................................................. 124 table conventions ............................................................................................................... 124 instruction defnition ................................................................................... 126 package information ................................................................................... 135 8-pin sop (150mil) outline dimensions ............................................................................. 136 10-pin sop (150mil) outline dimensions ........................................................................... 137 10-pin msop outline dimensions ...................................................................................... 138 16-pin nsop (150mil) outline dimensions ......................................................................... 139 20-pin dip (300mil) outline dimensions ............. ................................................................ 140 20-pin sop (300mil) outline dimensions ........................................................................... 142 20-pin ssop (150mil) outline dimensions ......................................................................... 143
rev. 1.71 6 april 11, 2017 rev. 1.71 7 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom features cpu features ? operating v oltage f sys = 8 mhz: 2. 2v~5.5v ? up to 0.5s instruction cycle with 8mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? two oscillators internal rc -- hirc internal 32khz -- lirc ? fully intergrated internal 8 mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 4-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 1k14/2k15 ? ram data memory: 648/968 ? true eeprom memory: 328 ? watchdog t imer function ? up to 18 bidirectional i/o lines ? software controlled 4-scom lines lcd driver with 1/2 bias (only available for ht66f004) ? multiple pin-shared external interrupts ? multiple t imer modules for time measure, compare match output, capture input, pwm output, single pulse output functions ? dual t ime-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? wide range of available package types ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years
rev. 1.71 6 april 11, 2017 rev. 1.71 7 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom general description the devices are flash memory type 8-bit high performance risc architecture microcontrollers. offering use rs t he c onvenience of fl ash me mory m ulti-programming fe atures, t hese de vices a lso include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter function. multiple and extremely flexible t imer mo dules p rovide t iming, p ulse g eneration, c apture i nput, c ompare m atch o utput, single pulse output and pwm generation functions. protective features such as an internal w atchdog timer and low v oltage res et coupled w ith excellent nois e immunity and es d protection ens ure that reliable operation is maintained in hostile electrical environments. a full choice of h irc and lirc os cillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vices wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most features are common to all devices, the main feature distinguishing them are program memory and data memory capacity. the following table summarises the main features of each device. part no. program memory data memory data eeprom i/o a/d converter timer module time base stack r-type lcd package HT66F002 1k14 648 328 8 12-bit4 10-bit stm1 2 2 8sop 10msop HT66F0025 2k14 648 328 8 12-bit4 10-bit stm1 2 4 8/10sop ht66f003 1k14 648 328 14 12-bit4 10-bit stm1 10-bit ptm1 2 2 16nsop ht66f004 2k15 968 328 18 12-bit8 10-bit ptm2 2 4 4scom 16nsop 20dip/sop 20ssop
rev. 1.71 8 april 11, 2017 rev. 1.71 9 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom block diagram 8-bit risc mcu core i/o time bases low voltage reset interrupt controller reset circuit 12-bit a/d converter ram data memory timer modules watchdog timer internal rc oscillators flash program memory eeprom data memory flash/eeprom programming circuitry note: lcd function is only available for ht66f004. pin assignment HT66F002 10 msop-a 10 9 8 7 6 1 2 3 4 5 vdd/avdd pa6/stp0i/[stck0] pa5/int/stp0b/an3 pa7/[int]/stck0/res/icpck pa4 vss/avss pa0/[stp0]/[stp 0i]/an0/icpda pa1/[stp0b]/an1/vref pa2/[int]/stp0/an2/vrefo pa3/[int] HT66F002/HT66F0025 8 sop-a vdd/avdd pa6/stp0i/[stck0] pa5/int/stp0b/an3 pa7/[int]/stc k0/res/icpck vss/avss pa0/[stp0]/[stp0i]/an0/icpda pa1/[stp0b]/an1/vref pa2/[int]/stp0/an2/vrefo 8 7 6 5 1 2 3 4 HT66F0025 10 sop-a 10 9 8 7 6 1 2 3 4 5 vdd/avdd pa6/stp0i/[stck0] pa5/int/stp0b/an3 pa7/[int]/stck0/res/icpck pa4 vss/avss pa0/[stp0]/[stp 0i]/an0/icpda pa1/[stp0b]/an1/vref pa2/[int]/stp0/an2/vrefo pa3/[int]
rev. 1.71 8 april 11, 2017 rev. 1.71 9 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom vdd/avdd pb2/ptck0/an2 pa4/ptck1/an3 pa5/an4/vref pa6/an5/vrefo pa7/ptp1/an6 pb3/scom3/an7 pb4/clo/scom2 ht66f004/ht66v004 20 sop-a/ssop-a/dip-a vss/avss pc0/scom0 pc1/scom1 pc2/res pa0/ptp0/icpda/ocdsda pa1/ptp0i pa2/icpck/ocdsck pa3/ptp1i pb6/ptp1b pb5/ptp0b pb0/int0/an0 pb1/int1/an1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ht66f004/ht66v004 16 nsop-a 16 15 14 13 12 11 10 9 2 3 4 5 6 7 8 1 vss/avss pc0/scom0 pc1/scom1 pc2/res pa0/ptp0/icpda/ocdsda pa1/ptp0i pa2/icpck/ocdsck pa3/ptp1i vdd/avdd pb2/ptck0/an2 pa4/ptck1/an3 pa5/an4/vref pa6/an5/vrefo pa7/ptp1/an6 pb0/int0/an0 pb1/int1/an1 ht66f003/ht66v003 16 nsop-a vss/avss pa0/[stp0i]/an 0/ocdsda/icpda pa1/an1/vref pa2/[int]/[stck0]/an2/ocdsck/icpck pa3/int/stck0/an3 vdd/avdd pa6/[ptck1]/stp0i/[stp0] pa5/[int]/ptp1i pa7/[ptck1]/[stp0b]/res pa4/[int]/ptck1/stp0 pb2/ptp1b pb1/[ptck1]/stp0b pb0/[ptp1i]/vrefo pb3/[ptp1] pb4/[ptp1b] pb5/ptp1 16 15 14 13 12 11 10 9 2 3 4 5 6 7 8 1 ht66v002/ht66v0025 16 nsop-a 16 15 14 13 12 11 10 9 vdd/avdd pa6/stp0i/[stck0] pa5/int/stp0b/an3 pa4 nc nc ocdsck pa7/[int]/stck 0/res/icpck vss/avss pa1/[stp0b]/an1/vref pa2/[int]/stp0/an2/vrefo pa3/[int] nc nc ocdsda pa0/[stp0]/[stp0i]/an0/icpda 2 3 4 5 6 7 8 1 note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. a vdd&vdd m eans t he vdd a nd a vdd a re t he d ouble bo nding. vss& avss m eans t he vss a nd avss are the double bonding. 3. the ocdsda and ocdsck pins are the ocds dedicated pins
rev. 1.71 10 april 11, 2017 rev. 1.71 11 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pin description with the exceptio n of the power pins and some relevant transformer control pins, all pins on these devices c an be re ferenced by t heir por t na me, e .g. p a0, p a1 e tc, whi ch re fer t o t he di gital i/ o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. HT66F002/HT66F0025 pin name function opt i/t o/t description pa0/[stp0]/ [stp0i]/an0/ icpda pa0 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up stp0 pasr cmos tm0 (stm) output stp0i pasr ifs0 st tm0 (stm) input an0 pasr an adc input channel 0 icpda st cmos icp data line pa1/[stp0b]/ an1/vref pa1 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up stp0b pasr cmos tm0 (stm) inverting output an1 pasr an adc input channel 1 vref pasr an adc vref input pa2/[ int]/ stp0/an2/ vrefo pa2 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input stp0 pasr cmos tm0 (stm) output an2 pasr an adc input channel 2 vrefo pasr an adc reference voltage output pa3/ [int] pa3 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input pa4 pa4 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up pa5/ int/ stp0b/an3 pa5 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input stp0b pasr cmos tm0 (stm) inverting output an3 pasr an adc input channel 3 pa6/stp0i/ [stck0] pa6 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up stp0i ifs0 st tm0 (stm) input stck0 ifs0 st tm0 (stm) clock input
rev. 1.71 10 april 11, 2017 rev. 1.71 11 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pin name function opt i/t o/t description pa7/[ int]/ stck0/res/ icpck pa7 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up int ifs0 st external interrupt input stck0 ifs0 st tm0 (stm) clock input res rstc st external reset input icpck st cmos icp clock line vdd vdd pwr digital positive power supply avdd avdd pwr analog positive power supply vss vss pwr digital negative power supply avss avss pwr analog negative power supply ocdsck ocdsck st on chip debug system clock line (ocds ev only) ocdsda ocdsda st cmos on chip debug system data line (ocds ev only) ht66f003 pin name function opt i/t o/t description pa0 /[stp0i]/ an0 /ocdsda/ icpda pa0 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up stp0i pasr ifs0 st tm0 (stm) input an0 pasr an adc input channel 0 ocdsda st cmos on chip debug system data line (ocds ev only) icpda st cmos icp data line pa 1/an1/vref pa 1 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up an1 pasr an adc input channel 1 vref pasr an adc vref input pa 2/[int]/ [stck0]/an2 /ocdsck/ icpck pa 2 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input stck0 ifs0 st tm0 (stm) clock input an2 pasr an adc input channel 2 ocdsck st on chip debug system clock line (ocds ev only) icpck st cmos icp clock line pa3/ int/ stck0/an3 pa3 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input stck0 ifs0 st tm0 (stm) clock input an3 pasr an adc input channel 3 pa4/[ int]/ ptck1/stp0 pa4 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input ptck1 pasr ifs0 st tm1 (ptm) clock input stp0 pasr cmos tm0 (stm) output
rev. 1.71 12 april 11, 2017 rev. 1.71 13 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pin name function opt i/t o/t description pa5/[ int]/ ptp1i pa5 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up int pasr ifs0 st external interrupt input ptp1i ifs0 st tm1 (ptm) input pa6/[ptck1]/ stp0i/[stp0] pa6 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up ptck1 pasr ifs0 st tm1 (ptm) clock input stp0i pasr ifs0 st tm0 (stm) input stp0 pasr cmos tm0 (stm) output pa7/[ptck1]/ [stp0b]/ res pa7 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up ptck1 pasr ifs0 st tm1 (ptm) clock input stp0b pasr st cmos tm0 (stm) inverting output res rstc st external reset input pb0/[ptp1i]/ vrefo pb0 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp1i pbsr ifs0 st tm1 (ptm) input vrefo pbsr an adc reference voltage output pb1/[ptck1]/ stp0b pb1 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptck1 pbsr ifs0 st tm1 (ptm) clock input stp0b pbsr st cmos tm0 (stm) inverting output pb2/ptp1b pb2 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp1b pbsr st cmos tm1 (ptm) inverting output pb3/[ptp1] pb3 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp1 pbsr cmos tm1 (ptm) output pb4/[ptp1b] pb4 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp1b pbsr cmos tm1 (ptm) inverting output pb5/ptp1 pb5 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp1 pbsr cmos tm1 (ptm) output vdd vdd pwr digital positive power supply avdd avdd pwr analog positive power supply vss vss pwr digital negative power supply avss avss pwr analog negative power supply
rev. 1.71 12 april 11, 2017 rev. 1.71 13 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ht66f004 pin name function opt i/t o/t description pa0/ptp0/ ocdsda/ icpda pa0 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up ptp0 pasr cmos pt0 output ocdsda st cmos on chip debug system data line (ocds ev only) icpda st cmos icp data line pa1/ptp0i pa1 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up ptp0i st ptm0 input pa2 /icpck/ ocdsck pa2 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up icpck st cmos icp clock line ocdsck st on chip debug system clock line (ocds ev only) pa3/ ptp1i pa3 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up ptp1i st ptm1 input pa4/ptck1/ an3 pa4 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up ptck1 pasr st ptm1 clock input an3 pasr an adc input channel 3 pa5/an4/vref pa5 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up an4 pasr an adc input channel 4 vref pasr an adc vref input pa6/an5/ vrefo pa6 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up an5 pasr an adc input channel 5 vrefo pasr an adc reference voltage output pa7/ptp1/an6 pa7 pawu papu pasr st cmos general purpose i/o. register enabled pull-up and wake-up ptp1 pasr cmos ptm1 output an6 pasr an adc input channel 6 pb0/int0/an0 pb0 pbpu pbsr st cmos general purpose i/o. register enabled pull-up int0 pbsr st external interrupt input an0 pbsr an adc input channel 0 pb1/int1/an1 pb1 pbpu pbsr st cmos general purpose i/o. register enabled pull-up int1 pbsr st external interrupt input an1 pbsr an adc input channel 1 pb2/ptck0/ an2 pb2 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptck0 pbsr st ptm0 clock input an2 pbsr an adc input channel 2
rev. 1.71 14 april 11, 2017 rev. 1.71 15 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pin name function opt i/t o/t description pb3/scom3/ an7 pb3 pbpu pbsr st cmos general purpose i/o. register enabled pull-up scom3 scomc scom lcd driver output for lcd panel common an7 pbsr an adc input channel 7 pb4/clo/ scom2 pb4 pbpu pbsr st cmos general purpose i/o. register enabled pull-up clo pbsr cmos system clock output scom2 scomc scom lcd driver output for lcd panel common pb5/ptp0b pb5 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp0b pbsr st cmos ptm0 inverting output pb6/ptp1b pb6 pbpu pbsr st cmos general purpose i/o. register enabled pull-up ptp1b pbsr st cmos ptm1 inverting output pc0/scom0 pc0 pcpu st cmos general purpose i/o. register enabled pull-up scom0 scomc scom lcd driver output for lcd panel common pc1/scom1 pc1 pcpu st cmos general purpose i/o. register enabled pull-up scom1 scomc scom lcd driver output for lcd panel common pc2/res pc1 pcpu rstc st cmos general purpose i/o. register enabled pull-up res rstc st external reset input vdd vdd pwr digital positive power supply avdd avdd pwr analog positive power supply vss vss pwr digital negative power supply avss avss pwr analog negative power supply legend: i/t: input type; o/t: output type; pwr: power; op: optional by register option scom: software controlled lcd com st: schmitt t rigger input; cmos: cmos output; an: analog pin *: vdd i s t he d evice p ower sup ply whi le a vdd i s t he adc p ower su pply. t he a vdd p in i s b onded together internally with vdd. **: vss i s t he d evice g round p in wh ile a vss i s t he adc g round p in. t he a vss p in i s b onded together internally with vss. absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability.
rev. 1.71 14 april 11, 2017 rev. 1.71 15 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom d.c. characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hirc) f sys =8mhz 2.2 5.5 v i dd1 operating current, normal mode, f sys =f h (hirc) 3v no load, f h =8mhz, adc off, wdt enable , lvr enable 1.0 2.0 ma 5v 2.0 3.0 ma i dd2 operating current, slow mode, f sys =f l =lirc 3v no load, f sys =lirc, adc off, wdt enable , lvr enable 20 30 a 5v 30 60 a i dd3 operating current, normal mode, f h =8mhz (hirc) 3v no load, f sys =f h /2, adc off, wdt enable , lvr enable 1.0 1.5 ma 5v 1.5 2.0 ma 3v no load, f sys =f h /4, adc off, wdt enable , lvr enable 0.9 1.3 ma 5v 1.3 1.8 ma 3v no load, f sys =f h /8, adc off, wdt enable , lvr enable 0.8 1.1 ma 5v 1.1 1.6 ma 3v no load, f sys =f h /16, adc off, wdt enable , lvr enable 0.7 1.0 ma 5v 1.0 1.4 ma 3v no load, f sys =f h /32, adc off, wdt enable , lvr enable 0.6 0.9 ma 5v 0.9 1.2 ma 3v no load, f sys =f h /64, adc off, wdt enable , lvr enable 0.5 0.8 ma 5v 0.8 1.1 ma i idle0 idle0 mode stan dby current (lirc on) 3v no load, adc off, wdt enable, lvr disable 1.3 3.0 a 5v 5.0 10 a i idle1 idle1 mode stan dby current (hirc) 3v no load, adc off, wdt enable, f sys =8mhz on 0.8 1.6 ma 5v 1.0 2.0 ma i sleep0 sleep0 mode standby current (lirc off) 3v no load, adc off, wdt disable, lvr disable 0.1 1.0 a 5v 0.3 2.0 a i sleep1 sleep1 mode standby current (lirc on) 3v no load, adc off, wdt enable, lvr disable 1.3 5.0 a 5v 2.2 10 a v il1 input low voltage for i/o ports or input pins except res pin 5v 0 1.5 v 0 0.2v dd v v ih1 input high voltage for i/o ports or input pins except res pin 5v 3.5 5.0 v 0.8v dd v dd v v il2 input low voltage ( res) 0 0.4v dd v v ih2 input high voltage ( res) 0.9v dd v dd v i ol i/o port sink current 3v v ol =0.1v dd 18 36 ma 5v v ol =0.1v dd 40 80 ma i oh i/o port, source current 3v v oh =0.9v dd -3 -6 ma 5v v oh =0.9v dd -7 -14 ma r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k i ocds operating current, normal mode, f sys =f h (hirc) (for ocds ev testing, connect to an e-link) 3v no load, f h =8 mhz, adc off, wdt enable 1.4 2.0 ma
rev. 1.71 16 april 11, 2017 rev. 1.71 17 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom a.c. characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd condition f cpu operating clock 2.2~5.5v dc 8 mhz f hirc system clock (hirc) 3v/5v ta = 25c -2% 8 +2% mhz 3v/5v ta = 0c to 70c -5% 8 +5% mhz 2.2v~5.5v ta = 0c to 70c -8% 8 +8% mhz 2.2v~5.5v ta = -40c to 85c -12% 8 +12% mhz f lirc system clock (lirc) 2.2v~5.5v ta = -40c to 85c 8 32 50 khz t timer xtckn, xtpni input pulse width 0.3 s t res external reset low pulse width 10 s t int interrupt pulse width 0.3 s t eerd eeprom read time 2 4 t sys t eewr eeprom write time 2 5 ms t sst system start-up timer period (wake-up from halt , f sys off at halt state ) f sys =hirc 16 t sys f sys =lirc 2 t rstd system reset delay time (power on reset, lvr reset, wdt s/w reset(wdtc) 25 50 100 ms system reset delay time (res reset, wdt normal reset) 8.3 16.7 33.3 ms 1rwh w sys i sys pdd kh dffdf i kh hdo food ihthf d hfso fdsdf ko be fhfh hhh 9 d 966 d ofdh d foh kh hyfh d soh
rev. 1.71 16 april 11, 2017 rev. 1.71 17 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom adc electrical characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d converter operating voltage 2.7 5.5 v v adi a/d converter input voltage 0 a v dd / v ref v v ref a/d converter reference voltage 3v 2 a v dd v 5v dnl differential non-linearity 2.7v v ref =av dd =v dd t adck =0.5s -3 +3 lsb 3v 5v inl integral non-linearity 2.7v v ref =av dd =v dd t adck =0.5s -4 +4 lsb 3v 5v i adc additional power consumption if a/d converter is used 3v no load (t adck =0.5s ) 1.0 2.0 ma 5v no load (t adck =0.5s ) 1.5 3.0 ma t adck a/d converter clock period 2.7~ 5.5v 0.5 10 s t adc a/d conversion time (include sample and hold time) 2.7~ 5.5v 12-bit adc 16 20 t adck t ads a/d converter sampling time 2.7~ 5.5v 4 t adck t on2st a/d converter on-to-start time 2.7~ 5.5v 4 s opa electrical characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions av dd opa operating voltage 2.7 5.5 v i opa opa operating current 5v no load 200 350 a v opos1 input offset voltage 5v -15 15 mv v cm common mode voltage range 5v 0.2 v dd -1.4 v psrr power supply rejection ratio 5v 60 80 db cmrr common mode rejection ratio 5v 60 80 db sr slew rate +, slew rate - 5v 0.8 1.5 v/s gbw gain band width 5v 500 khz errg opa gain error 5v gain=1/2/3/4 if opa input voltage 0.2v -5 gain +5 %
rev. 1.71 18 april 11, 2017 rev. 1.71 19 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom lvr electrical characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 1.9 5.5 v v lvr low voltage reset voltage lvr enable, 2.1v option -5% 2.10 +5% v v bg reference output with buffer t j = +25c @3.15v -5% 1.04 +5% v t lvr low voltage width to reset 160 320 640 s lcd electrical characteristics C ht66f004 symbol parameter test conditions min. typ. max. unit v dd conditions i bias v dd /2 bias current for lcd 5v isel[1:0]=00 17.5 25.0 32.5 a isel[1:0]=01 35 50 65 a isel[1:0]=10 70 100 130 a isel[1:0]=11 140 200 260 a v scom v dd /2 voltage for lcd com port 2.2~5.5v no load 0.475 0.5 0.525 v dd power on reset electrical characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr por v dd rising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms
rev. 1.71 18 april 11, 2017 rev. 1.71 19 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device take s advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility . this makes these devices suitable for low-cost, high-volume production for controller applications clocking and pipelining the main system clock, derived from either a hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? system clock and pipelining
rev. 1.71 20 april 11, 2017 rev. 1.71 21 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register HT66F002/ht66f003 pc9~pc8 pcl7~pcl0 HT66F0025/ht66f004 pc10~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.71 20 april 11, 2017 rev. 1.71 21 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.
device stack levels HT66F002/ht66f003 2 HT66F0025/ht66f004 4 arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation : rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement : inca, inc, deca, dec ? branch decision : jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.71 22 april 11, 2017 rev. 1.71 23 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for th ese device s the program memory are flash type, which means it can be programmed and re-programmed a lar ge number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices of fer users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. device capacity HT66F002/ht66f003 1k 14 HT66F0025 2k 14 ht66f004 2k 15 structure the program memory has a capacity of 1 k1 4, 2 k14 or 2k15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. 000h initialisation vector 004h 3 ffh 14 bits interrupt vectors look - up table n 00h nffh ht 66f 002 initialisation vector 14 bits interrupt vectors look - up table initialisation vector 15 bits interrupt vectors look - up table 7 ffh 01 ch ht 66 f 003 ht 66f 004 018h initialisation vector 14 bits interrupt vectors look - up table ht 66f 0025 7 ffh program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by th ese device s reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp . th is register defne s the total address of the look-up table. after setting up the table pointer , the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] i nstructions, re spectively. w hen t he i nstruction i s e xecuted, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0.
rev. 1.71 22 april 11, 2017 rev. 1.71 23 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom the accompanying diagram illustrates the addressing data fow of the look-up table.

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? table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 3 00h which refers to the start address of the last page within the 1 k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 3 06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the specifed page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 3 06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 3 05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 3 00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.71 24 april 11, 2017 rev. 1.71 25 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4 -pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. holtek write pins mcu programming pins function HT66F002/HT66F0025 ht66f003/ht66f004 icpda pa 0 programming serial data icpck pa7 pa2 programming serial clock vdd vdd power supply vss vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 4 -wire inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and ground . the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. ht 66f 002/ ht 66 f 0025 * * writer _ vdd icpda icpck writer _ vss to other circuit vdd pa 0 pa 7 vss writer connector signals mcu programming pins ht 66 f 003/ ht 66f 004 * * writer _ vdd icpda icpck writer _ vss to other circuit vdd pa 0 pa 2 vss writer connector signals mcu programming pins 1rwh pd eh uhvlvwru ru fdsdflwr u 7kh uhvlvwdfh ri pxvw eh juhdwhu wkd n ru wkh fdsdflwdfh ri pxvw eh ohvv wkd ) on-chip debug support C ocds there is an ev chip which is used to emulate the ht66f00x device series. this ev chip device also provides an on-chip debug function to debug the device during the development process. the ev chip and the actual mcu devices are almos t functionally compatible except for the on- chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda p in i s t he oc ds da ta/address i nput/output p in wh ile t he oc dsck p in i s t he oc ds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pi ns in the actual mcu devi ce will have no ef fect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide.
rev. 1.71 24 april 11, 2017 rev. 1.71 25 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip debug support data/address input/output ocdsck ocdsck on-chip debug support clock input vdd vdd power supply gnd vss ground ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. general purpose data memory there is 64 or 96 bytes of general purpose data memory which are arranged in bank 0 and bank1. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user programing for both reading and wr iting o perations. b y u sing t he b it o peration i nstructions i ndividual b its c an b e se t o r r eset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory . special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h. device capacity bank 0 bank 1 HT66F002/HT66F0025/ht66f003 648 40h~7fh 40h eec register only ht66f004 968 40h~9fh 40h eec register only
rev. 1.71 26 april 11, 2017 rev. 1.71 27 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 00h iar0 01h mp0 02h iar1 03h mp1 04h 05h acc 06h pcl 07h tblp 08h tblh 09h intc1 0ah status 0bh 0ch 0dh 0eh 0fh 10h smod 11h eea 12h 19h 18h 1bh 1ah 1dh 1ch 1fh 1eh 13h 14h 15h 16h 17h integ unused stm0al papu pawu 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2eh ~ 3fh 23h 24h 25h 26h 27h bp stm0dl stm0c1 stm0dh pa pac stm0c0 intc0 : unused, read as 00 eed unused unused stm0ah unused unused mfi0 unused unused ifs0 wdtc tbc smod1 pasr rstc sadc1 sadc0 sadc2 sadol sadoh unused unused bank0 & bank1 bank0 & bank1 HT66F002/HT66F0025 special purpose data memory structure
rev. 1.71 26 april 11, 2017 rev. 1.71 27 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 00h iar0 01h mp0 02h iar1 03h mp1 04h 05h acc 06h pcl 07h tblp 08h tblh 09h intc1 0ah status 0bh 0ch 0dh 0eh 0fh 10h smod 11h eea 12h 19h 18h 1bh 1ah 1dh 1ch 1fh 1eh 13h 14h 15h 16h 17h integ unused stm0al papu pawu 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2eh 23h 24h 25h 26h 27h bp stm0dl stm0c1 stm0dh pa pac stm0c0 intc0 : unused, read as 00 eed unused unused stm0ah unused unused mfi0 unused ifs0 wdtc tbc smod1 pasr rstc sadc1 sadc0 sadc2 sadol sadoh bank0 & bank1 bank0 & bank1 ptm1ah ptm1dh ptm1dl ptm1al ptm1c1 ptm1rpl pbpu pbc pb 33h 32h 35h 34h 37h 36h 38h 2fh 30h 31h ptm1rph 39h unused ptm1c0 unused 3ah ~ 3fh mfi1 pbsr ht66f003 special purpose data memory structure
rev. 1.71 28 april 11, 2017 rev. 1.71 29 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 00h iar0 01h mp0 02h iar1 03h mp1 04h 05h acc 06h pcl 07h tblp 08h tblh 09h intc1 0ah status 0bh 0ch 0dh 0eh 0fh 10h smod 11h eea 12h 19h 18h 1bh 1ah 1dh 1ch 1fh 1eh 13h 14h 15h 16h 17h integ scomc ptm0dh papu pawu 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2eh 23h 24h 25h 26h 27h bp ptm0c1 ptm0c0 ptm0dl pa pac intc0 : unused, read as 00 eed unused unused ptm0al unused unused mfi0 unused wdtc tbc smod1 pasr rstc sadc1 sadc0 sadc2 sadol sadoh bank0 & bank1 bank0 & bank1 ptm1ah ptm1dh ptm1dl ptm1al ptm1c1 ptm1rpl ptm0rph ptm0rpl 33h 32h 35h 34h 37h 36h 38h 2fh 30h 31h ptm1rph 39h ptm0ah ptm1c0 pbsr unused unused unused unused pcc pbpu pbc pc pb pcpu 3ah 3ch 3bh 3dh 3eh 3fh ht66f004 special purpose data memory structure unused eec general purpose data memory 40 h 7 fh unused eec general purpose data memory 40 h 9 fh ht 66 f 002 / ht 66 f 0025 / ht 66 f 003 ht 66 f 004 HT66F002/HT66F0025/ht66f003 general purpose data memory
rev. 1.71 28 april 11, 2017 rev. 1.71 29 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.71 30 april 11, 2017 rev. 1.71 31 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom bank pointer C bp for this series of device s , the data memory is divided into two banks , bank0 and bank1 . selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addressi ng the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank 1 must be implemented using indirect a ddressing. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 b it 7 ~ 1 unimplemented, read as "0" b it 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user - defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the program memory . tblp is the table pointer and indicate the location where the table data is located. its value must be setup before any table read commands are executed. its value can b e c hanged, f or e xample u sing t he inc o r dec i nstructions, a llowing f or e asy t able d ata pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.71 30 april 11, 2017 rev. 1.71 31 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.71 32 april 11, 2017 rev. 1.71 33 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 "" unknown b it 7~6 unimplemented, read as "0" b it 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. b it 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction b it 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest- order bit or vice versa. b it 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero b it 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction b it 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. eeprom data memory these devices contain an area of i nternal e eprom da ta me mory. e eprom, wh ich st ands f or electrically erasable programmable read only memory , is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of d ata m emory, a wh ole n ew h ost o f a pplication p ossibilities a re m ade a vailable t o t he d esigner. the a vailability o f e eprom st orage a llows i nformation su ch a s p roduct i dentifcation n umbers, calibration values , s pecifc us er data, s ystem s etup data or other product information to be s tored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eep rom d ata m emory capacity is 32 8 b its for this series of devices. u nlike the p rogram memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using two address registers and one data register in bank 0 and a single control register in bank 1.
rev. 1.71 32 april 11, 2017 rev. 1.71 33 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register s , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ~ 5 unimplemented, read as 0 b it 4 ~ 0 data eeprom address data eeprom address bit 4 ~ bit 0 eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0
rev. 1.71 34 april 11, 2017 rev. 1.71 35 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as "0" b it 3 wren : data eeprom w rite enable 0: disable 1: enable this is the data eeprom w rite enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. b it 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this is the data eeprom w rite control bit and when set high by the applicat ion program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. b it 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. b it 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applicat ion program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he r d bi t t o de termine whe n t he da ta i s valid for reading.
rev. 1.71 34 april 11, 2017 rev. 1.71 35 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frs t be cleared before implementing any write operat ions, and then set agai n aft er the write cyc le has start ed. note that setting the wr bi t high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent w rite operation is provided in several ways . after the device s are powered-on the w rite enable bit in the control register will be cleared preventing any write operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom interrupt are enabled and the stack is not full, a subroutine call to the eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the eeprom interrupt fag def will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.71 36 april 11, 2017 rev. 1.71 37 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycl e starts. n ote that the devices should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. o therwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom - polling method 029((3520b5(6 hhhdh 02 02 hhlh03 0203 03lhlh 02 hd3lh 023 6,5 h51elhdehhdhdl 6,5 d5hdfhh5el back: 6,5 ; check for read cycle end -03. /5,5 ldeh3520lh /53 02 ; move read data to register 025b ? writing data to the eeprom - polling method 029((3520b5(6 hhhdh 02 023520b hhhdd 02 02 hhlh03 0203 03lhlh 02 hd3lh 023 /5 0, 6,5 h:51elhdehlhhdl 6,5 d:lhfhh:5elhhfhlhldhdh h:51el 60, back: 6,5 ; check for write cycle end -03. /5,5 ldeh3520lh /53
rev. 1.71 36 april 11, 2017 rev. 1.71 37 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he watchdog t imer a nd t ime b ase i nterrupts. two f ully i ntegrated i nternal o scillators, r equiring no extern al components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillator p rovide s h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillator . with the capability of dynamically switching between fast and slow system clock, the se device s have the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed rc hirc 8mhz internal low speed rc lirc 32khz oscillator types system clock confgurations there are two m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a low spee d oscillator. the high speed oscillator is the internal 8mhz rc oscillato r. the low speed oscillator is the intern al 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. hirc prescaler f h lirc low speed oscillation f h /2 f h / 16 f h / 64 f h /8 f h /4 f h / 32 hlclk cks2~cks 0 bits f sys f l high speed oscillation system clock confgurations
rev. 1.71 38 april 11, 2017 rev. 1.71 39 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal rc o scillator h as a f ixed f requenc y o f 8 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at temperature of 25c degrees, the fxed oscillation frequency of the hirc will have a tolerance within 2%. internal 32khz oscillator C lirc the i nternal 3 2khz sy stem osc illator i s t he l ow f requency o scillator. i t i s a f ully i ntegrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. supplementary oscillator the low speed oscillator, in addition to providing a system clock source is also used to provide a clock source to two other device functions. these are the w atchdog timer and the t ime b ase interrupts. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided these device s with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks these device s ha ve two dif ferent clock sources for both the cpu and peripheral function operation. by providing the user with clock options using register programming, a clock system can be confgured to obtain maximum application performance. the m ain syst em c lock, c an c ome from e ither a hi gh fre quency, f h , or a low fre quency, f l , a nd i s selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from hirc oscillator . the low speed system clock source can be sourced from the internal clock f l . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there is one additional internal clock for the peripheral circuits, the t ime base clock, f tbc . f tbc i s sourced fr om t he l irc osc illators. t he f tbc clock i s use d a s a so urce fo r t he t ime b ase i nterrupt functions and for the tms.
rev. 1.71 38 april 11, 2017 rev. 1.71 39 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom hirc prescaler f h lirc low speed oscillation f h /2 f h / 16 f h / 64 f h /8 f h /4 f h / 32 hlclk cks2~cks 0 bits f sys f lirc high speed oscillation wdt f sys /4 f tb time base 0 time base 1 tbck f l f tbc idlen system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep 0 , sleep 1, idle0 a nd i dle1 m ode s a re u sed wh en t he m icrocontroller c pu i s swi tched o ff t o conserve power. operating mode description cpu f sys f lirc f tbc normal mode on f h ~f h /64 on on slow mode on f l on on idle0 mode off off on on idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of it s functi ons operati onal and where the system clock is provide d the high speed oscil lator. this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the h igh sp eed o scillator hirc. t he h igh sp eed o scillator wi ll h owever fr st b e d ivided b y a r atio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current.
rev. 1.71 40 april 11, 2017 rev. 1.71 41 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from the low speed oscil lator lirc . running the micro controller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f lirc clock will be stopped too, and the w atchdog t imer function is disabled. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep 1 mode the cpu will be stopped. however the f lirc clocks will continue to operate if the w atchdog t imer function is enabled . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode, the watchdog timer clock, f lirc , will be on. control register a single register, smod , is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 b it 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source.
rev. 1.71 40 april 11, 2017 rev. 1.71 41 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom bit 4 unimplemented, read as "0" b it 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode, but after a wake-up has occurred the fag will change to a high level after 1~2 cycles if the lirc oscillator is used. b it 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then c hanges t o a h igh l evel a fter t he h igh sp eed sy stem o scillator i s st able. t herefore t his fa g will always be read as 1 by the application program after device power-on. b it 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low , the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. b it 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. smod1 register bit 7 6 5 4 3 2 1 0 name fsyson d3 lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown b it 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0 bit 3 d3 : reserved bit b it 2 lvrf : lvr function reset fag 0: n ot active 1: active this bit can be clear to 0, but can not be set to 1. b it 1 unimplemented, read as 0
rev. 1.71 42 april 11, 2017 rev. 1.71 43 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom b it 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is s et to 1 by the wdt control register s oftware reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. operating mode switching the d evice s c an swi tch b etween o perating m odes d ynamically a llowing t he u ser t o se lect t he b est performance/power ratio for the pres ent tas k in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction . when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms.
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rev. 1.71 42 april 11, 2017 rev. 1.71 43 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se t ting t he hlclk bit to 0 and set ting the cks2~cks0 bits to 000 or 001 in the smod register .this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
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rev. 1.71 44 april 11, 2017 rev. 1.71 45 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked.
? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? - ? ? ?? ? ? ???? ? - ? ? ?? ? ? ? ?? ? entering the sleep 0 mode there is only one way for the devic e s to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.71 44 april 11, 2017 rev. 1.71 45 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom entering the sleep 1 mode there is only one way for the devic e s to enter the sleep 1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt on . when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction , but the wdt will remain with the clock source coming from the f lirc clock . ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in smod1 register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruc - tion, but the t ime base clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the devic e s to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in smod1 register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.71 46 april 11, 2017 rev. 1.71 47 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device s to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. spe cial a ttention m ust be m ade t o the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any floating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must eit her be set up as out puts or if set up as input s must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps . wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, i f the se device s are woken up by a wdt overflow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, t he actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.71 46 april 11, 2017 rev. 1.71 47 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer c lock sourc e i s prov ided by t he i nternal f lirc c lock wh ich i s supplied by t he lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer tim eouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the wdt can be enabled/disabled using the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation . the wrf software reset fag will be indicated in the smod1 register . these registers control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 b it 7~ 3 we4 ~ we0 : wdt function software control 10101: wdt disable 01010: wdt enable other values: reset mcu when these bits are changed to any other values by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit will be set to 1 to indicate the reset source . b it 2~ 0 ws2 ~ ws0 : wdt t ime - out period selection 000: 2 8 / f lirc 001: 2 9 /f lirc 010: 2 10 /f lirc 011: 2 1 1 /f lirc (default) 100: 2 12 /f lirc 101: 2 13 /f lirc 110: 2 14 /f lirc 111: 2 15 /f lirc these three bits dete rmine the division ratio of the w atchdog t imer sourece clock, which in turn determines the timeout period.
rev. 1.71 48 april 11, 2017 rev. 1.71 49 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom smod1 register bit 7 6 5 4 3 2 1 0 name fsyson d3 lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown b it 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0 bit 3 d3 : reserved bit b it 2 lvrf : lvr function reset fag 0: n ot active 1: active this bit can be clear to 0, but can not be set to 1. b it 1 unimplemented, read as 0 b it 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction s will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. with regard to the w atchdog t imer enable/disable function, t here are fve bits, we4~we0, in the wdtc register to additional enable /disable and reset control of the watchdog t imer . we4 ~ we0 bits wdt function 10101b disable 01010b enable any other value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a value other than 01010b and 10101b is written into the we4~we0 bit locations , the second is an external hardware reset, which means a low level on the external reset pin , t he third is using the w atchdog t imer software clear instructions and the fourth is via a hal t instruction. there is only one method of using software instruction to clear the watchdog t imer. that is to use the single clr wdt instruction to clear the wdt .
rev. 1.71 48 april 11, 2017 rev. 1.71 49 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom the maximum time-out period is when the 2 15 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdt instruction 11- stage divider 7- stage divider we 4~ we 0 bits wdtc register reset mcu lirc f l irc 8- to - 1 mux clr ws 2~ ws 0 (f lirc /2 1 ~ f lirc /2 11 ) wdt time - out (2 8 /f l irc ~ 2 15 /f l irc ) res pin reset halt instruction watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device s can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in a ddition t o t he p ower-on r eset, si tuations m ay a rise where i t i s n ecessary t o f orcefully a pply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low . in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold.
rev. 1.71 50 april 11, 2017 rev. 1.71 51 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom reset functions there are several w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally : power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=50ms power-on reset timing chart res pin reset although t he m icrocontroller ha s a n i nternal rc re set func tion, i f t he v dd powe r suppl y ri se t ime is not fas t enough or does not s tabilise quickly at pow er-on, the internal res et function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operat ion of the microcont roller will be inhibited. aft er the res line rea ches a cert ain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer. for most applicati ons a resistor connected between v dd and the res pin and a capacitor connected between vss and the res pin will provide a suitable externa l reset circuit. any wiring connecte d to the res pin should be kept as short as possible to minimize any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection ** it is recomm ended that this component is added in environments where power line noise is signifcant external res circuit
rev. 1.71 50 april 11, 2017 rev. 1.71 51 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom more information regarding externa l reset circuits is located in application note ha0075e on the holtek website. pulling t he res pi n l ow u sing e xternal h ardware wi ll a lso e xecute a d evice r eset. i n t his c ase, a s i n t he case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time= 16.7ms res reset timing chart ? rstc external reset register C HT66F002/ht66f003 bit 7 6 5 4 3 2 1 0 name rstc7 rstc6 rstc5 rstc4 rstc3 rstc2 rstc1 rstc0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 rst c7 ~ rstc0 : p a7/res selection 01010101: confgured as p a 7 pin or other function 10101010: confgured as res pin other v alues: inhibit to use all reset will reset this register as por value except wdt time out hardware warm reset. ? rstc external reset register C ht66f004 bit 7 6 5 4 3 2 1 0 name rstc7 rstc6 rstc5 rstc4 rstc3 rstc2 rstc1 rstc0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 rstc7 ~ rstc0 : pc2/ res selection 01010101: confgured as pc2 pin or other function 10101010: confgured as res pin other v alues: inhibit to use all reset will reset this register as por value except wdt time out hardware warm reset. low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the devi ce and provide an mcu reset should the value fall below a certain predefned level. the lvr function is always enabled during the normal and slow modes with a specifc l vr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~ v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the smod1 register will also be set to1 . f or a valid l vr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed this value , the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr is 2.1v , the l vr will reset the device after 2~3 lirc clock cycles. note that the lvr function will be automatically disabled when the device enters the sleep/idle mode. note:t rstd is power-on delay, typical time=50ms low voltage reset timing chart
rev. 1.71 52 april 11, 2017 rev. 1.71 53 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? smod1 register bit 7 6 5 4 3 2 1 0 name fsyson d3 lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown b it 7 fsyson : f sys control in idle mode describe elsewhere bit 6~4 unimplemented, read as 0 bit 3 d3 : reserved bit b it 2 lvrf : lvr function reset fag 0: n ot active 1: active this bit can be clear to 0, but can not be set to 1. b it 1 unimplemented, read as 0 b it 0 wrf : wdt control register software reset fag describe elsewhere watchdog time-out reset during normal operation the w atchdog tim e-out reset during normal operation is the same as a n lvr reset except that the watchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart
rev. 1.71 52 april 11, 2017 rev. 1.71 53 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer modules timer modules will be turned off input/output ports i/o ports will be setup as inputs and an0~an3 as a/d input pins stack pointer stack pointer will point to the top of the stack
rev. 1.71 54 april 11, 2017 rev. 1.71 55 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. register HT66F002 HT66F0025 ht66f003 ht66f004 reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* program counter 000h 000h 000h 000h 000h mp0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu mp1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu smod 000- 0011 000- 0011 000- 0011 000- 0011 uuu- uuuu integ ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs0 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu 0000 0-00 0000 0-00 0000 0-00 0000 0-00 uuuu u-uu wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 0011 -111 uuuu Cuuu smod1 0--- 0x-0 0--- 0x-0 0--- 0x-0 0--- 0x-0 u--- uu-u scomc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu eea ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu sadol (adrfs=0) xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- sadol (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu
rev. 1.71 54 april 11, 2017 rev. 1.71 55 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom register HT66F002 HT66F0025 ht66f003 ht66f004 reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* sadc0 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 -000 0000 -000 0000 -000 0000 -000 uuuu -uuu sadc1 000- -000 000- -000 000- -000 000- -000 uuu- -uuu sadc2 00-- 0000 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu rstc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu pasr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pbsr --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu stm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu stm0al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm0al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm0rpl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0rph ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm1c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm1al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm1rpl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1rph ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu pb --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu pbc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu pbpu --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu pc ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pcc ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pcpu ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu eec ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: " *" stands for warm reset "-" not implement "u" stands for "unchanged" "x" stands for "unknown"
rev. 1.71 56 april 11, 2017 rev. 1.71 57 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device s provide bidirectional input/output lines labeled with port names p a~pc. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o control register list ? HT66F002/HT66F0025 register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pawu d7 d6 d5 d4 d3 d2 d1 d0 pas r pas7 pas6 pas5 pas4 pas3 pas2 pas1 pas0 ifs0 stck0ps stp0ips intps1 intps0 ? ht66f003 register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pawu d7 d6 d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pasr pas7 pas6 pas5 pas4 pas3 pas2 pas1 pas0 pbsr pbs5 pbs4 pbs3 pbs2 pbs1 pbs0 ifs0 ptck1ps1 ptck1ps0 stck0ps stp0ips ptp1ips intps1 intps0
rev. 1.71 56 april 11, 2017 rev. 1.71 57 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? ht66f004 register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pawu d7 d6 d5 d4 d3 d2 d1 d0 pb d6 d5 d4 d3 d2 d1 d0 pbc d6 d5 d4 d3 d2 d1 d0 pbpu d6 d5 d4 d3 d2 d1 d0 pc d2 d1 d0 pcc d2 d1 d0 pcpu d2 d1 d0 pasr pas7 pas6 pas5 pas4 pas3 pas2 pas1 pas0 pbsr pbs6 pbs5 pbs4 pbs3 pbs2 pbs1 pbs0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using register papu ~pcpu , and are implemented using weak pmos transistors. p apu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable pbpu register C ht66f003 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7~ 6 unimplemented, read as 0 b it 5~0 i/o port b bit 5 ~ bit 0 pull-high control 0: disable 1: enable pbpu register C ht66f004 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~0 i/o port b bit 6~ bit 0 pull-high control 0: disable 1: enable
rev. 1.71 58 april 11, 2017 rev. 1.71 59 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pcpu register C ht66f004 bit 7 6 5 4 3 2 1 0 name d2 d1 d0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2~0 i/o port c bit 2~ bit 0 pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port a bit 7 ~ bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac ~pcc , to control the input/output configuration. w ith t h ese c ontrol re gister s , e ach cmos out put or i nput c an be re configured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input
rev. 1.71 58 april 11, 2017 rev. 1.71 59 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pbc register C ht66f003 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 b it 7 ~ 6 unimplemented, read as 0 b it 5 ~ 0 i/o port b bit 5 ~ bit 0 input/output control 0: output 1: input pbc register C ht66f004 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 bit 7 unimplemented, read as 0 bit 6~0 i/o port b bit 6 ~ bit 0 input/output control 0: output 1: input pcc register C ht66f004 bit 7 6 5 4 3 2 1 0 name d2 d1 d0 r/w r/w r/w r/w por 1 1 1 bit 7~3 unimplemented, read as 0 bit 2~0 i/o port c bit 2 ~ bit 0 input/output control 0: output 1: input pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established where more than one pin function is selected simultaneously . additionally there are a p asr and a pbsr register to establish certain pin functions. generally speaking, the analog function has higher priority than the digital function. however , if more than two analog functions are enabl ed and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules.
rev. 1.71 60 april 11, 2017 rev. 1.71 61 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom pin-shared registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. ? pasr register C HT66F002/HT66F0025 bit 7 6 5 4 3 2 1 0 name pas7 pas6 pas5 pas4 pas3 pas2 pas1 pas0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas7~pas6 : pin-shared control bits 00: pa5/ int 01: stp0b 10: pa5/ int 11: an3 bit 5~4 pas5~pas4: pin-shared control bits 00: pa2/ int 01: stp0 10: vrefo 11: an2 bit 3~2 pas3~pas2: pin-shared control bits 00: pa1 01: stp0b 10: vref 11: an1 bit 1~0 pas1~pas0: pin-shared control bits 00: pa0/stp0i 01: stp0 10: pa0/stp0i 11: an0
rev. 1.71 60 april 11, 2017 rev. 1.71 61 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? p asr register C ht66f003 bit 7 6 5 4 3 2 1 0 name pas7 pas6 pas5 pas4 pas3 pas2 pas1 pas0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 p as7: pin-shared control bit 0: pa7/ptck1 1: stp0b note: pas7 is valid when rstc=55h b it 6 p as6: pin-shared control bit 0: pa6/ptck1/stp0i 1: stp0 b it 5 p as5: pin-shared control bit 0: pa4/ int/ptck1 1: stp0 b it 4 p as4: pin-shared control bit 0: pa3/ int/stck0 1: an3 bit 3 pas3: pin-shared control bit 0: pa2/ int/stck0 1: an2 bit 2~1 pas2~pas1: pin-shared control bits 0x: pa1 10: vref 11: an1 bit 0 pas0 : pin-shared control bit 0: pa0/stp0i 1: an0 ? pasr register C ht66f004 bit 7 6 5 4 3 2 1 0 name pas7 pas6 pas5 pas4 pas3 pas2 pas1 pas0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas7~pas6 : pin-shared control bit 00: pa7 01: ptp1 10: pa7 11: an6 bit 5~4 pas5~pas4 : pin-shared control bit 0x: pa6 10: vrefo 11: an5 bit 3~2 p as3~ pas2 : pin-shared control bit 0x: pa5 10: vref 11: an4 bit 1 pas1 : pin-shared control bits 0: pa4/ptck1 1: an3 bit 0 pas0 : pin-shared control bit 0: pa0 1: ptp0
rev. 1.71 62 april 11, 2017 rev. 1.71 63 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? pbsr register C ht66f003 bit 7 6 5 4 3 2 1 0 name pbs5 pbs4 pbs3 pbs2 pbs1 pbs0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7~6 unimplemented, read as 0 b it 5 pbs5: pin-shared control bit 0: pb5 1: ptp1 b it 4 pbs4: pin-shared control bit 0: pb4 1: ptp1b b it 3 pbs3: pin-shared control bit 0: pb3 1: ptp1 bit 2 pbs2: pin-shared control bit 0: pb2 1: ptp1b bit 1 pbs1: pin-shared control bits 0: pb1/ptck1 1: stp0b bit 0 pbs0 : pin-shared control bit 0: pb0/ptp1i 1: vrefo ? pbsr register C ht66f004 bit 7 6 5 4 3 2 1 0 name pbs6 pbs5 pbs4 pbs3 pbs2 pbs1 pbs0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 pbs6 : pin-shared control bit 0: pb6 1: ptp1b bit 5 pbs5 : pin-shared control bit 0: pb5 1: ptp0b bit 4 pbs4 : pin-shared control bit 0: pb4 1: clo note: pbs4 is valid when com2en=0 bit 3 pbs3 : pin-shared control bit 0: pb3 1: an7 note: pbs3 is valid when com3en=0 bit 2 pbs2 : pin-shared control bit 0: pb2/ptck0 1: an2 bit 1 pbs1 : pin-shared control bits 0: pb1/int1 1: an1 bit 0 pbs0 : pin-shared control bit 0: pb0/int0 1: an0
rev. 1.71 62 april 11, 2017 rev. 1.71 63 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? ifs0 register C HT66F002/HT66F0025 bit 7 6 5 4 3 2 1 0 name stck0ps stp0ips intps1 intps0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 stck0ps : stck0 pin remapping control 0: stck0 on pa7 (default) 1: stck0 on pa6 bit 4 stp0ips : stp0i pin remapping control 0: stp0i on pa 6 (default) 1: stp0i on pa 0 bit 3~2 unimplemented, read as "0" bit 1~0 intps1, intps0 : int pin remapping control 00: int on pa5 (default) 01: int on pa2 10: int on pa 3 11: int on p a7 ? ifs0 register C ht66f003 bit 7 6 5 4 3 2 1 0 name ptck1ps1 ptck1ps0 stck0ps stp0ips ptp1ips intps1 intps0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7~6 ptck1ps1, ptck1ps0: ptck1 pin remapping control 00: ptck1 on pa4 (default) 01: ptck1 on pa6 10: ptck1 on pa7 11: ptck1 on pb1 bit 5 stck0ps: stck0 pin remapping control 0: stck0 on pa 3 (default) 1: stck0 on pa 2 bit 4 stp0ips: stp0i pin remapping control 0: stp0i on pa 6 (default) 1: stp0i on pa 0 bit 3 ptp1ips: ptp1i pin remapping control 0: ptp1i on pa5 (default) 1: ptp1i on pb0 bit 2 unimplemented, read as "0" bit 1~0 intps1, intps0: int pin remapping control 00: int on pa 3 (default) 01: int on pa2 10: int on pa 4 11: int on p a5
rev. 1.71 64 april 11, 2017 rev. 1.71 65 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure
rev. 1.71 64 april 11, 2017 rev. 1.71 65 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom system clock output pin clo the device ht66f004 provides a system clock output pin clo. mcu system clock can output to the c lo p in b y se tting p in-shared c ontrol r egister b it pb s4 t o 1 . t he h ighest o utput f requency i s 8mhz in this device. please note that when the noise problem is an important issue, it is better not to use clo output function. programming considerations within the user program, one of the frs t things to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input stat e, the level of whi ch de pends on the ot her connected circuitry and whe ther pull - high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data regis ters are frst programmed. selecting which pins are inputs and which are outputs can be achieved byt e-wide by l oading t he c orrect va lues i nto t he a ppropriate port c ontrol re gister or by programming individual bi ts i n t he port c ontrol re gister usi ng t he set [m ].i a nd clr [m ].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.71 66 april 11, 2017 rev. 1.71 67 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device s include several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual standard and periodic tm section s. introduction the devic e s conta in one or two tms depending upon which device is selected with each tm having a reference name of tm0~tm1. each individual tm can be categori sed as a certain type, namely standard t ype tm or periodic t ype tm. although similar in nature, the dif ferent tm types vary in their feat ure complexity . the comm on features to the standard and periodic tms will be described in this section and the detailed operation will be described in corresponding sections. the main features and differences between the two types of tms are summarised in the accompanying table. function stm ptm timer/counter i/p capture compare match output pwm channels 1 1 single pulse output 1 1 pwm alignment edge edge pwm adjustment period & duty duty or period duty or period tm function summary device tm0 tm1 HT66F002/HT66F0025 10-bit stm ht66f003 10-bit stm 10-bit ptm ht66f004 10-bit ptm 10-bit ptm tm name/type reference tm operation the two different t ypes o f t m s o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the xtnck2~xtnck0 bits in the xtm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external x tckn pin. the x tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting.
rev. 1.71 66 april 11, 2017 rev. 1.71 67 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom tm interrupts the standard and periodic type tms each has two internal interrupts, the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has two tm input pin s , with the label x tckn and xtpni . the tm input pin x tckn, is essentially a clock source for the tm and is selected using the xtnck2~xtnck0 bits in the x tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the xtnck2~x tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. t he other tm input pin, xtpni, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the xtnio1 and xtnio0 bits in the xtmnc1 register. the tms each ha ve two output pins with the label x tpn and xtpnb . when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the externa l x tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type is dif ferent, the details are provided in the accompanying table. device tm0 tm1 HT66F002/HT66F0025 stck0, stp0i stp0, stp0b ht66f003 stck0, stp0i stp0, stp0b ptck1, ptp1i ptp1, ptp1b ht66f004 ptck0, ptp0i ptp0, ptp0b ptck1, ptp1i ptp1, ptp1b tm input/output pins tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , w ith a s ingle bit in each register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. stm stp0 stck0 capture input tck input output stp0i stp0b inverting output s tm function pin control block diagram
rev. 1.71 68 april 11, 2017 rev. 1.71 69 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ptm ptpn ptckn capture input tck input output ptpni ptpnb inverting output p tm function pin control block diagram programming considerations the tm counter registers and the capture/compare ccra register , and ccrp register pair for periodic t imer module , all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra register and ccrp registers are implemented in the way shown in the following diagram and accessing the register is carried o ut ccrp low byte register using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. 8- bit buffer p tmndh p tmndl p tmn rp h p tmn rp l p tmnah p tmnal p tm counter register ( read only ) p tm ccra register ( read / write ) p tm ccr p register ( read / write ) data bus 8- bit buffer stm dh stm dl stm 0 ah stm 0 al stm counter register ( read only ) stm ccra register ( read / write ) data bus 7kh iroorzlj vwhsv vkrz wkh uhdg dg zulwh surfhgxuhv :ulwlj 'dwd wr &&5 ru 370 &&53 ? step 1. w rite data to low byte stm 0 al ptmnal or ptmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte stm 0 ah ptmnah or ptmnrph C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ptm ccrp ? step 1. read data from the high byte stm 0 dh, stm 0 ah ptmndh, ptmnah or ptmnrph C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte stm 0 dl, stm 0 al ptmndl, ptmnal or ptmnrpl C this step reads data from the 8-bit buffer.
rev. 1.71 68 april 11, 2017 rev. 1.71 69 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can be controlled with two external input pins and can drive two external output pins. device tm type tm name tm input pin tm output pin HT66F002 HT66F0025 ht66f003 10-bit stm stm stck0, stp0i stp0, stp0b
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? ? ? ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? standard type tm block diagram standard tm operation at its core is a 1 0 -bit count-up counter which is driven by a user selectable internal clock source. there are also tw o internal comparators w ith the names , comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. t he ccrp is 3- bit wide whose value is compared with the highest 3 bits in the counter while the ccra is the 10 bits and therefore compares with all counter bits. the onl y way of changing the value of the 1 0 -bit count er using the appl ication program , is to clear the counter by changing the st0 on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.71 70 april 11, 2017 rev. 1.71 71 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom standard type tm register description overall operation of the standard tm is controlled using series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 1 0 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 1 0 -bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as three ccrp bits . name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stm0c0 st0 pau st0ck2 st0ck1 st0ck0 st0on st0rp2 st0rp1 st0rp0 stm0c1 st0m1 st0m0 st0io1 st0io0 st0oc st0pol st0dpx st0cclr stm0dl d7 d6 d5 d4 d3 d2 d1 d0 stm0dh d9 d8 stm0al d7 d6 d5 d4 d3 d2 d1 d0 stm0ah d9 d8 10-bit standard tm register list stm0c0 register bit 7 6 5 4 3 2 1 0 name st0pau st0ck2 st0ck1 st0ck0 st0on st0rp2 st0rp1 st0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 st0pau : stm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the stm will remain powered up and continue to consume power . the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 st0ck2~st0ck0 : select stm counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: stck0 rising edge clock 111: stck0 falling edge clock these three bits are used to select the clock source for the stm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 st0on : stm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the stm. setting the bit high enables the counter to r un, c learing t he b it d isables t he st m. c learing t his b it t o z ero wi ll st op t he c ounter f rom counting and turn of f the stm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high a gain. i f t he st m i s i n t he c ompare ma tch ou tput mo de o r t he pw m o utput mo de o r single pulse output mode then the stm output pin will be reset to its initial condition, as specifed by the st0oc bit, when the st0on bit changes from low to high.
rev. 1.71 70 april 11, 2017 rev. 1.71 71 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom bit 2~0 st0rp2~ st0rp0 : stm ccrp 3-bit register, compared with the stm counter bit 9~bit 7 comparator p match period 000: 1024 stm0 clocks 001: 128 stm0 clocks 010: 256 stm0 clocks 011: 384 stm0 clocks 100: 512 stm0 clocks 101: 640 stm0 clocks 110: 768 stm0 clocks 111: 896 stm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the st0cclr bit is set to zero. setting the st0cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in ef fect allowing the counter to overfow at its maximum value. stm0c1 register bit 7 6 5 4 3 2 1 0 name st0m1 st0m0 st0io1 st0io0 st0oc st0pol st0dpx st0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~6 st0m1~ st0m0 : select stm0 operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the stm. t o ensure reliable operation the stm should be switched off before any changes are made to the st0m1 and st0m0 bits. in the t imer/ counter mode, the stm output pin state is undefned. bit 5 ~4 st0io1~ st0io0: select stm0 function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stp0i 01: input capture at falling edge of stp0i 10: input capture at falling/rising edge of stp0i 11: input capture disabled timer/counter mode: unused these t wo bi ts a re use d t o de termine how t he t m out put pi n c hanges st ate whe n a c ertain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.71 72 april 11, 2017 rev. 1.71 73 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom in the compare match output mode, the st0io1~st0 io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the st0io1~st0io0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the st0oc bit . note that the output level requested by the s t 0 io1~st 0 io0 bits must be dif ferent from the initial value setup using the st0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the st0on bit from low to high. in t he pw m mo de, t he s t 0 io1 a nd s t 0 io0 b its d etermine h ow t he t m o utput p in c hanges state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the st0 io1 and st0 io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the s t 0 io1 and st0 io0 bits are changed when the tm is running . bit 3 st0oc : stm0 output control bit compare match output mode 0: initial low 1: initial high pwm output mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the stm output pin. its operation depends upon whether stm is being used in the compare match output mode or in the pwm output mode/ single pulse output mode. it has no ef fect if the stm is in the t imer/counter mode. in the compare match output mode it dete rmines the logic level of the stm output pin before a compare match occurs. in t he pw m ou tput mo de i t d etermines i f t he pw m si gnal i s a ctive h igh or a ctive l ow. i n t he single pulse output mode it determines the logic level of the stm output pin when the st0on bit changes from low to high . bit 2 st0pol : stm0 output polarity control 0: non-invert 1: invert this bit controls the polarity of the stm0 output pin. when the bit is set high the stm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the stm is in the t imer/ counter mode. bit 1 st0dpx : stm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 st0cclr : select stm0 counter clear condition 0: stm0 comparator p match 1: stm0 comparator a match this bit is used to select the method which clears the counter . remember that the standard stm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the st0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the st0cclr bit is not used in the pwm output mode, single pulse or input capture mode.
rev. 1.71 72 april 11, 2017 rev. 1.71 73 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom stm0 dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 stm0 counter low byte register bit 7 ~ bit 0 stm0 10-bit counter bit 7 ~ bit 0 stm0dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 stm0 counter high byte register bit 1 ~ bit 0 stm0 10-bit counter bit 9 ~ bit 8 stm0al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stm0 ccra low byte register bit 7 ~ bit 0 stm0 10-bit counter bit 7 ~ bit 0 stm0ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 stm0 ccra high byte register bit 1 ~ bit 0 stm0 10-bit counter bit 9 ~ bit 8
rev. 1.71 74 april 11, 2017 rev. 1.71 75 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the st0m1 and st0m0 bits in the stm 0 c1 register. compare output mode to select this mode, bits st0m1 and st0m0 in the stm 0 c1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the st0cclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both stma0f and stmp0f interrupt request fags for comparator a and comparator p respectively, will both be generated. if the st0cclr bit in the stm 0 c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the stma0f interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when st0cclr is high no stmp0f interrupt request flag will be generated. in the compare match output mode, the ccra can not be set to "0". if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the stma 0 f interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the stm output pin, will change state. the stm output pin condition however only changes state when an stma0f interrupt request fag is generated after a compare match occurs from comparator a. the stmp0f interrupt request fag, g enerated f rom a c ompare m atch o ccurs f rom c omparator p , wi ll h ave n o e ffect o n t he st m output pin. the way in which the stm output pin changes state are determined by the condition of the st0io1 and st0io0 bits in the stm 0 c1 register . the stm output pin can be selected using the st 0io1 a nd st 0io0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from comparator a. the initial condition of the stm output pin, which is setup afte r the st0on bit changes from low to high, is setup using the st0oc bit. note that if the st0io1 and st0io0 bits are zero then no pin change will take place.
rev. 1.71 74 april 11, 2017 rev. 1.71 75 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ccra ccrp 0x3 ff counter overflow ccra int . flag stma 0f ccrp int . flag stmp 0f ccrp > 0 counter cleared by ccrp value stm o/ p pin st 0 on pause counter reset output pin set to initial level low if st0 oc = 0 output toggle with stma0f flag here st 0 io [1:0 ] = 11 toggle output select now st 0 io [1:0 ] = 10 active high output select output not affected by stma0f flag . remains high until reset by st0 on bit st0 cclr = 0 ; st0m[1:0 ] = 00 st 0 pau resume stop time ccrp > 0 ccrp = 0 st 0 pol output pin reset to initial value output inverts when st0pol is high output controlled by other pin - shared function counter value compare match output mode C st0cclr = 0 note: 1. w ith st0 cclr = 0 a comparator p match will clear the counter 2. the tm output pin controlled only by the s tma0 f fag 3. the o utput pin reset to initial state by a s t0 on bit rising edge
rev. 1.71 76 april 11, 2017 rev. 1.71 77 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ccra ccrp 0x3 ff ccra int . flag stmp 0f ccrp int . flag stma 0f ccra > 0 counter cleared by ccra value stm o/ p pin st 0 on pause counter reset output pin set to initial level low if st0 oc = 0 output toggle with stma0f flag here st 0 io [1:0 ] = 11 toggle output select now st 0 io [1:0 ] = 10 active high output select output not affected by stma0f flag . remains high until reset by st0 on bit st0 cclr = 1 ; st0m[1:0 ] = 00 st 0 pau resume stop time ccra = 0 st 0 pol output pin reset to initial value output inverts when st0pol is high output controlled by other pin - shared function counter value output does not change no stma 0 f flag generated on ccra overflow ccra = 0 counter overflow stmp0 f not generated compare match output mode C st0cclr = 1 note: 1. w ith st 0 cclr = 1 a comparator a match will clear the counter 2. the tm output pin controlled only by the stma 0 f fag 3. the output pin reset to initial state by a st 0 on rising edge 4. the stmp 0 f fag is not generated when st 0 cclr = 1
rev. 1.71 76 april 11, 2017 rev. 1.71 77 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom timer/counter mode to se lect t his mode , bi ts st 0m1 and st 0m0 i n t he st m 0 c1 regi ster should be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the stm output pin is not used. therefore the above description and t iming diagrams for the compare match out put mod e c an be use d t o un derstand i ts fu nction. as t he st m ou tput pi n i s no t use d i n this mode, the pin can be used as a normal i/o pin or other pin-shared function by setting pin-share function register. pwm output mode to select this mode, bits st0m1 and st0m0 in the stm 0 c1 register should be set to 10 respectively and also the st0io1 and st0io0 bits should be set to 10 respectively . the pwm function within the stm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. in t he pw m output mode, t he st 0cclr bi t ha s no e ffect a s t he pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or dut y c ycle i s de termined usi ng t he st 0dpx bi t i n t he st m 0 c1 re gister. t he pw m wa veform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the st0oc bit in the stm 0 c1 register is used to select the required polari ty of the pwm waveform whi le the two st0io1 and st0io0 bi ts are used to enable the p wm output or to force the s tm output pin to a f xed high or low level. the st0pol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit stm, pwm output mode, edge-aligned mode, st0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the stm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/ 512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit stm, pwm output mode, edge-aligned mode, st0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the stm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.71 78 april 11, 2017 rev. 1.71 79 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ccrp ccra counter value counter cleared by ccrp ccra int . flag stma 0f ccrp int . flag stmp 0f stm o / p pin ( st 0 oc =1) st 0 on pwm duty cycle set by ccra pwm period set by ccrp counter stop if st 0 on bit low counter reset when st 0 on returns high pwm resumes operation output controlled by other pin - shared function time st0dpx=0;st0m[1:0 ]= 10 st 0 pol output inverts when st 0 pol = 1 st 0 pau resume pause stm o / p pin ( st 0 oc =0) pwm output mode C st0dpx = 0 note: 1. here st0 dpx = 0 - counter cleared by ccrp 2. a c ounter c lear sets pwm period 3. the i nternal pwm function continues running even when st0 io[1:0] = 00 or 01 4. the s t0 cclr bit has no infuence on pwm operation
rev. 1.71 78 april 11, 2017 rev. 1.71 79 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ccra ccrp counter value counter cleared by ccra ccrp int . flag stmp 0f ccra int . flag stma 0f stm o / p pin ( st 0 oc =1) st 0 on pwm duty cycle set by ccrp pwm period set by ccra counter stop if st 0 on bit low counter reset when st 0 on returns high pwm resumes operation output controlled by other pin - shared function time st0dpx=1;st0m[1:0 ]= 10 st 0 pol output inverts when st 0 pol = 1 st 0 pau resume pause stm o / p pin ( st 0 oc =0) pwm output mode C st0dpx = 1 note: 1. here st0 dpx = 1 - counter cleared by ccra 2. a c ounter c lear sets pwm period 3. the i nternal pwm function continues even when st0 io[1:0] = 00 or 01 4. the s t0 cclr bit has no infuence on pwm operation
rev. 1.71 80 april 11, 2017 rev. 1.71 81 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom single pulse mode to select this mode, bits st 0 m1 and st 0 m0 in the stm 0 c1 register should be set to 10 respectively and also the st 0 io1 and st 0 io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the stm output pin. the t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he st 0 on b it, wh ich can be implement ed using the application program. however in the single pulse mode, the st 0 on bit can also be made to automatically change from low to high using the external stck 0 pin, which will in turn initiate the single pulse output. when the st 0 on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the st 0 on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the st 0 on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. s/w command setst0on or stck0 pin transition trailing edge s/w command clrst0on or ccra compare match stp0/stp0b output pin pulse width = ccra value leading edge st0on bit 0 1 st0on bit 1 0 single pulse generation
rev. 1.71 80 april 11, 2017 rev. 1.71 81 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom counter value ccrp ccra st 0 on st 0 pau st 0 pol ccrp int . flag stmp0f ccra int . flag stma0f stm o / p pin ( st 0 oc =1) time counter stopped by ccra pause resume counter stops by software counter reset when st0 on returns high st 0 m [1:0 ] = 10 ; st 0 io [1:0 ] = 11 pulse width set by ccra output inverts when st 0 pol = 1 no ccrp interrupts generated stm o / p pin ( st 0 oc =0) stck 0 pin software trigger cleared by ccra match stck 0 pin trigger auto. set by stck 0 pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the p ulse is triggered by setting the s t0 on bit high 4 . in the single pulse mode, st0 io [1:0] must be set to 11 and can not be changed. however a compa re match from comparator a will also automatically clear the st 0 on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stm interrupt. the counter can only be res et back to zero w hen the st 0 on bit changes from low to high w hen the counter restarts. in the single pulse mode ccrp is not used. the st 0 cclr and st 0 dpx bits are not used in this mode.
rev. 1.71 82 april 11, 2017 rev. 1.71 83 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom capture input mode to select this mode bits st 0 m1 and st 0 m0 in the stm 0 c1 register should be set to 01 respectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the stp 0 i, whose active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the st 0 io1 and st 0 io0 bits in the stm 0 c1 register . the counter is started when the st 0 on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the stp 0 i the present value in the counter will be latched into the ccra registers and a stm interrupt generated. irrespective of what events occur on the stp 0 i the counter will continue to free run until the st 0 on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a stm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the st 0 io1 and st 0 io0 bits can select the active trigger edge on the stp 0 i to be a rising edge, falling edge or both edge types. if the st0 io1 and st 0 io0 bits are both set high, then no capture operation will take place irrespective of what happens on the stp 0 i, however it must be noted that the counter will continue to run. the st 0 cclr and st 0 dpx bits are not used in this mode. counter value yy ccrp st 0 on st 0 pau ccrp int . flag stmp0f ccra int . flag stma0f ccra value time counter cleared by ccrp pause resume counter reset st 0 m [1:0 ] = 01 stm capture pin stp 0i xx counter stop st 0 io [1:0 ] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capture capture input mode note: 1. st 0 m[1:0] = 01 and active edge set by the st 0 io[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the s t0 cclr and s t0 dpx bits are not used 4. no output function C st0 oc and st0 pol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.71 82 april 11, 2017 rev. 1.71 83 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with two external input pins and can drive two external output pins. device name tm input pin tm output pin ht66f003 10-bit ptm ptck1, ptp1i ptp1,ptp1b ht66f004 10-bit ptm ptck0, ptp0i ptck1, ptp1i ptp0,ptp0b ptp1,ptp1b periodic tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the ptnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.71 84 april 11, 2017 rev. 1.71 85 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 ptmnc0 ptnpau ptnck2 ptnckn ptnck0 ptnon ptmncn ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncks ptncclr ptmndl d7 d6 d5 d4 d3 d2 d1 d0 ptmndh d9 d8 ptmnal d7 d6 d5 d4 d3 d2 d1 d0 ptmnah d9 d8 ptmnrpl d7 d6 d5 d4 d3 d2 d1 d0 ptmnrph d9 d8 10-bit periodic tm register list (n=0 or 1) ptmnc0 register bit 7 6 5 4 3 2 1 0 name ptnpau ptnck2 ptnck1 ptnck0 ptnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 pt n pau : p tm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a p ause condition the tm w ill remain pow ered up and continue to consume power . the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 ptnck2~ptnck0 : select p tm counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: ptckn rising edge clock 111: ptckn falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be ac tive on the risi ng or fal ling edge. the cl ock sourc e f sys is the syst em cl ock, while f tbc is an other internal clock, the details of which can be found in the oscillator section.
rev. 1.71 84 april 11, 2017 rev. 1.71 85 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom bit 3 ptnon : p tm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the inte rnal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. bit 2~0 unimplemented, read as 0 ptmnc1 register bit 7 6 5 4 3 2 1 0 name ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncks ptncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pt nm1~ ptnm0 : select ptm operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched off before any changes are made to the pt n m1 and pt n m0 bits. in the t imer/ counter mode, the ptm output pin state is undefned. bit 5~4 pt nio1~ ptnio0 : select ptm output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of pt pni 01: input capture at falling edge of pt pni 10: input capture at falling/rising edge of pt pni 11: input capture disabled timer/counter mode unused these t wo bi ts a re use d t o de termine how t he t m out put pi n c hanges st ate whe n a c ertain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.71 86 april 11, 2017 rev. 1.71 87 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom in the compare match output mode, the pt n io1 and pt n io0 bits determine how the tm output pin changes state when a compare matc h occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when these bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the pt n oc bit. note that the output level requested by the p t 1 io1 and p t n io0 bits must be dif ferent from the initial value setup using the pt n oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the pt n on bit from low to high. in t he pw m mo de, t he pt n io1 a nd pt n io0 b its d etermine h ow t he t m o utput p in c hanges state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the pt n io1 and pt n io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the pt n io1 and ptn io0 bits are changed when the tm is running. bit 3 pt noc : pt pn/ptpn b output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 pt npol : pt pn/ptpn b output polarity control 0: non-invert 1: invert this bi t c ontrols t he p olarity of t he pt pn /pt pn b o utput pi n. w hen t he bi t i s se t h igh t he t m output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 pt ncks : ptm capture trigger source select 0: from pt pni 1: from ptck n pin bit 0 pt ncclr : select ptm counter clear condition 0: ptm comparatror p match 1: ptm comparatror a match this bit is used to select the method which clears the counter . remember that the periodic tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the pt n cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptn cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.71 86 april 11, 2017 rev. 1.71 87 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ptmn dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 ptm ndl : ptm counter low byte register bit 7 ~ bit 0 ptm 10-bit counter bit 7 ~ bit 0 ptmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptm ndh : ptm counter high byte register bit 1 ~ bit 0 ptm 10-bit counter bit 9 ~ bit 8 ptmn al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptm nal : ptm ccra low byte register bit 7 ~ bit 0 ptm 10-bit ccra bit 7 ~ bit 0 ptmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptm nah : ptm ccra high byte register bit 1 ~ bit 0 ptm 10-bit ccra bit 9 ~ bit 8 ptmn rpl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptm nrpl : ptm ccrp low byte register bit 7 ~ bit 0 ptm 10-bit ccrp bit 7 ~ bit 0
rev. 1.71 88 april 11, 2017 rev. 1.71 89 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ptm nrph register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 ptm nrph : ptm ccrp high byte register bit 1 ~ bit 0 ptm 10-bit ccrp bit 9 ~ bit 8 periodic type tm operating modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the ptnm1 and ptnm0 bits in the ptmnc1 register. compare match output mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register , should be all cleared to 00 r espectively. i n t his m ode o nce t he c ounter i s e nabled a nd r unning i t c an b e c leared b y t hree methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ptncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are a ll z ero whi ch a llows t he c ounter t o o verfow. he re b oth t he pt manf a nd pt mpnf i nterrupt request fags for comparator aand comparator p respectively, will both be generated. if the ptncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the ptma n f interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptncclr is high no ptmpnf interrupt request flag will be generated. in the compare match output mode, the ccra can not be set to 0. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ptma n f interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a ptmanf interrupt request fag is generated after a compare match occurs from comparator a. the ptmpnf interrupt request fag, generated from a compare match from comparator p , will have no ef fect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the ptnio1 and ptnio0 bits in the ptm nc1 register . the tm output pin can be selected using the ptnio1 and ptnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the ptnon bi t changes from low to hi gh, is setup using the ptnoc bi t. note tha t if the ptnio1, ptnio0 bits are zero then no pin change will take place.
rev. 1.71 88 april 11, 2017 rev. 1.71 89 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom counter value 0x3 ff ccrp ccra pt n on pt n pau pt n pol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm o / p pin time ccrp =0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart pt n cclr = 0 ; pt n m [1:0 ] = 00 output pin set to initial level low if pt n oc =0 output toggle with ptma n f flag note pt n io [1:0 ] = 10 active high output select here pt n io [1:0 ] = 11 toggle output select output not affected by ptma n f flag . remains high until reset by pt n on bit output pin reset to initial value output controlled by other pin - shared function output inverts when pt n pol is high compare match output mode C ptncclr = 0 (n=0 or 1) note: 1. w ith ptn cclr = 0 C a comparator p match will clear the counter 2. the tm output pin is controlled only by the ptman f fag 3. the output pin is reset to initial state by a ptn on bit rising edge
rev. 1.71 90 april 11, 2017 rev. 1.71 91 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom counter value 0x3 ff ccrp ccra pt n on pt n pau pt n pol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm o / p pin time ccra =0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart pt n cclr = 1 ; pt n m [1:0 ] = 00 output pin set to initial level low if pt n oc =0 output toggle with ptma n f flag note pt n io [1:0 ] = 10 active high output select here pt n io [1:0 ] = 11 toggle output select output not affected by tn af flag . remains high until reset by pt n on bit output pin reset to initial value output controlled by other pin - shared function output inverts when pt n pol is high ptmpnf not generated no ptma n f flag generated on ccra overflow output does not change compare match output mode C ptncclr = 1 (n=0 or 1) note: 1. w ith ptn cclr = 1 C a comparator a match will clear the counter 2. the tm output pin is controlled only by the p tman f fag 3. the output pin is reset to initial state by a ptn on rising edge 4. the ptmpn f fag is not generated when ptn cclr = 1
rev. 1.71 90 april 11, 2017 rev. 1.71 91 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom timer/counter mode to s elect this mode, bits p tnm1 and p tnm0 in the p tmnc1 regis ter s hould all be s et to 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively and also the ptnio1 and ptnio0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. in t he pw m m ode, t he pt ncclr bi t ha s no e ffect a s t he pw m period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycl e. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs fr om either comparator a or comparator p. t he ptnoc bit in the ptmnc1 register is used to select the required polarity of the pwm waveform while the two ptnio1 and ptnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the ptnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit pwm mode, edge-aligned mode ccrp ccrp = 0~1024 period ccrp=0 : period= 1024 clocks ccrp=1~1023: period=1~1023 clocks duty ccra if f sys = 16mhz, ptm clock source select f sys /4, ccrp = 512 and ccra = 128, the p tm pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.71 92 april 11, 2017 rev. 1.71 93 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom counter value ccrp ccra pt n on pt n pau pt n pol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm o / p pin ( pt n oc =1) time counter cleared by ccrp pause resume counter stop if ptn on bit low counter reset when ptn on returns high pt n dpx = 0 ; pt n m [1:0 ] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin - shared function output inverts when pt n pol = 1 pwm period set by ccrp ptm o / p pin ( pt n oc =0) pwm output mode (n=0 or 1) note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptn io[1:0] = 00 or 01 4. the ptn cclr bit has no infuence on pwm operation
rev. 1.71 92 april 11, 2017 rev. 1.71 93 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom single pulse output mode to select this mode, the required bit pairs, ptnm1 and ptnm0 should be set to 10 respectively and also the corresponding ptnio1 and ptnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he pt non b it, wh ich can be implement ed using the application program. however in the single pulse mode, the ptnon bit can also be made to automatically change from low to high using the external ptckn pin, which will in turn initiate the single pulse output. when the ptnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the ptnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ptnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compa re match from comparator a will also automatically clear the ptnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate tm interrupts. the counter can only be res et back to zero w hen the ptno n bit changes from low to high w hen the counter restarts. in the single pulse mode ccrp is not used. the ptncclr bit is also not used. ptn on bit 0 ? 1 s/ w command set ptn on or p tck n pin transition ptn on bit 1 ? 0 trailing edge s/ w command clr ptn on or ccra compare match p tp n/p tp n b output pin pulse width = ccra value leading edge single pulse generation (n=0 or 1)
rev. 1.71 94 april 11, 2017 rev. 1.71 95 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom counter value ccrp ccra pt n on pt n pau pt n pol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm o / p pin ( pt n oc =1) time counter stopped by ccra pause resume counter stops by software counter reset when ptn on returns high pt n m [1:0 ] = 10 ; pt n io [1:0 ] = 11 pulse width set by ccra output inverts when pt n pol = 1 no ccrp interrupts generated ptm o / p pin ( pt n oc =0) ptck n pin software trigger cleared by ccra match ptck n pin trigger auto. set by ptck n pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptckn pin or by setting the ptn on bit high 4. a ptckn pin active edge will automatically set the ptn on bit high 5. in the single pulse mode, ptn io [1:0] must be set to 11 and can not be changed.
rev. 1.71 94 april 11, 2017 rev. 1.71 95 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom capture input mode to select this mode bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 01 respectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and c an t herefore be use d fo r a pplications suc h a s pu lse wi dth m easurements. t he e xternal si gnal is supplie d on the ptpni or ptckn pin, selected by the ptncks bit in the ptmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is select ed using the ptnio1 and ptnio0 bits in the ptmnc1 register . the counter is started when the ptnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptpni or ptckn pin the present value in the counter will be latched into the ccra register and a tm interrupt generated. irrespective of what events occur on the ptpni or ptckn pin the counter will continue to free run until the ptnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptnio1 and ptnio0 bits can select the active trigger edge on the ptpni or ptckn pin to be a rising edge, falling edge or both edge types. if the ptnio1 and ptnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptpni or ptckn pin, however it must be noted that the counter will continue to run. as the ptpni or ptckn pin is pin shared with other functions, care must be taken if the ptm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptncclr, ptnoc and ptnpol bits are not used in this mode.
rev. 1.71 96 april 11, 2017 rev. 1.71 97 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom counter value yy ccrp pt n on pt n pau ccrp int . flag ptmpnf ccra int . flag ptmanf ccra value time counter cleared by ccrp pause resume counter reset pt n m [1:0 ] = 01 ptm capture pin pt pni or ptckn xx counter stop pt n io [1:0 ] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capture capture input mode (n=0 or 1) note: 1. ptn m[1:0] = 01 and active edge set by the ptn io[1:0] bits 2. a tm capture input pin active edge transfers counter value to ccra 3. the ptn cclr bit is not used 4. no output function C ptn oc and ptn pol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.71 96 april 11, 2017 rev. 1.71 97 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device s contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains and sacs bit felds. note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly configured except the sains and sacs bit fie lds. more det ailed i nformation a bout t he a/ d i nput si gnal i s desc ribed i n t he a/d converter control registers and a/d converter input signal sections respectively. part no. input channels a/d channel select bits input pins HT66F002 HT66F0025 ht66f003 4 sains2~sains0, sacs1~sacs0 an0~an3 ht66f004 8 sains2~sains0, sacs2~sacs0 an0~an7 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. an 0 an 5 an 6 an 7 12 - bit sar adc enadc sadoh [7:0] sadol [7:0] adbz saint sacs [2:0] v bg (1. 04 v) vref v ri divider f sys sacks [2:0] av dd savrs [3:0] v r vrefo sains [2:0] sapin vrefo enopa pasr opa mux pin - shared selection av dd v r a/d converter structure
rev. 1.71 98 april 11, 2017 rev. 1.71 99 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom a/d converter register description overall operation of the a /d converter is controlled us ing fve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 sadol (adrfs=0) d3 d2 d1 d0 sadol (adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 sadoh (adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 sadoh (adrfs=1) d11 d10 d9 d8 sadc0 start adbz enadc adrfs sacs1 sacs0 sadc1 sains2 sains1 sains0 sack2 sack1 sack0 sadc2 enopa vbgen savrs3 savrs2 savrs1 savrs0 a/d converter register list C HT66F002/HT66F0025/ht66f003 name bit 7 6 5 4 3 2 1 0 sadol (adrfs=0) d3 d2 d1 d0 sadol (adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 sadoh (adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 sadoh (adrfs=1) d11 d10 d9 d8 sadc0 start adbz enadc adrfs sacs2 sacs1 sacs0 sadc1 sains2 sains1 sains0 sacks2 sacks1 sacks0 sadc2 enopa vbgen savrs3 savrs2 savrs1 savrs0 a/d converter register list C ht66f004 a/d converter data registers C sadol, sadoh as the devices contain an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompanying table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. note that the a/d converter data register contents will not be cleared to zero if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a/d data registers
rev. 1.71 98 april 11, 2017 rev. 1.71 99 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom a/d converter control registers C sadc0, sadc1, sadc 2, pasr, pbsr to control the function and operation of the a/d converter , several control registers known as sadc0 , sadc1 and sadc2 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter , the digitised data format, t he a/ d c lock so urce a s we ll a s c ontrolling t he st art f unction a nd m onitoring t he a/ d converter busy status. the sacs2~sacs0 bits in the sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. if the sains2~sains0 bits are set to 000, the external analog channel input is selected to be converted and the sacs2~sacs0 bits can determine which external channel is selected to be converted. if the sains2~sains0 bits are set to 001 ~011 , the av dd voltage is selected to be converted. if the sains2~sains0 bits are set to 101 ~111 , the op a output voltage is selected to be converted. when v ref or v bg is selected as adc input or adc reference voltage, the opa needs to be enabled by setting enopa to 1. note that w hen the program s select external signal and internal signal as an adc input signal simultaneously , then the hardware will only choose the internal signal as an adc input. in addition, if the programs select external reference voltage v ref and the internal reference voltage v bg as adc reference voltage, then the hardware will only choose the internal reference voltage v bg as an adc reference voltage input. the pin-shared function control registers, named p as r and pbs r , contain the corresponding pin- shared s election bits w hich determine w hich pins on p ort a and p ort b are us ed as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in additio n, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. ? sadc0 register C HT66F002/HT66F0025/ht66f003 bit 7 6 5 4 3 2 1 0 name start adbz enadc adrfs sacs1 sacs0 r/w r/w r r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start a/d conversion 01: reset the a/d converter and set adbz to 0 10: start a/d conversion and set adbz to 1 bit 6 adbz : adc busy fag 0: a/d conversion ended or no conversion 1: a/d is busy bit 5 enadc : adc enable/disable control register 0: adc disable 1: adc enable bit 4 adrfs : a/d output data format selection bit 0: adc output data format sadoh=d[11:4]; sadol=d[3:0] 1: adc output data format sadoh=d[11:8]; sadol=d[7:0] bit 3~2 unimplemented, read as "0" bit 1~0 sacs1~sacs0 : adc input channels selection 00: adc input channel comes from an0 01: adc input channel comes from an1 10: adc input channel comes from an2 11: adc input channel comes from an3
rev. 1.71 100 april 11, 2017 rev. 1.71 101 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? sadc0 register C ht66f004 bit 7 6 5 4 3 2 1 0 name start adbz enadc adrfs sacs2 sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 01 0: start a/d conversion 0 1: reset the a/d converter and set adbz to 0 1 0: start a/d conversion and set adbz to 1 bit 6 adbz : adc busy fag 0: a/d conversion ended or no conversion 1: a/d is busy bit 5 enadc : adc enable/disable control register 0: adc disable 1: adc enable bit 4 adrfs : a/d output data format selection bit 0: adc output data format sadoh=d[11:4]; sadol=d[3:0] 1: adc output data format sadoh=d[11:8]; sadol=d[7:0] bit 3~2 unimplemented, read as 0 bit 1~0 sacs2~sacs0 : adc input channels selection 000: adc input channel comes from an0 001: adc input channel comes from an1 010: adc input channel comes from an2 011: adc input channel comes from an3 100: adc input channel comes from an4 101: adc input channel comes from an5 110: adc input channel comes from an6 111: adc input channel comes from an7 ? sadc1 register bit 7 6 5 4 3 2 1 0 name sains2 sains1 sains0 sacks2 sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~5 sains2~sains0 : internal adc input channel selection bit 000: adc input only comes from external pin 001: adc input also comes from a v dd 010: adc input also comes from a v dd /2 011: adc input also comes from a v dd /4 101: adc input also comes from v r 110: adc input also comes from v r /2 111: adc input also comes from v r /4 other v alues: same as 000 note: v r is op a output voltage. v r can be one of v ref /v ref 2/v ref 3/v ref 4/v bg 2/ v bg 3/ v bg 4. bit 4~3 unimplemented, read as "0" bit 2~0 sacks2~sacks0 : adc clock rate selection bit 000: saclk=f sys 001: saclk=f sys /2 010: saclk=f sys /4 011: saclk=f sys /8 100: saclk=f sys /16 101: saclk=f sys /32 110: saclk=f sys /64 111: saclk=f sys /128
rev. 1.71 100 april 11, 2017 rev. 1.71 101 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ? sadc2 register bit 7 6 5 4 3 2 1 0 name enopa vbgen savrs3 savrs2 savrs1 savrs0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 enopa : opa enable/disable control register 0: opa disable 1: opa enable bit 6 vbgen : bandgap buffer disable/enable control bit 0: bandgap buffer disable 1: bandgap buffer enabl e bit 5~4 unimplemented, read as "0" bit 3~0 savrs3~savrs0 : adc reference voltage selection bit 0000: adc reference voltage comes from a v dd 0001: adc reference voltage comes from v ref 0010: adc reference voltage comes from v ref 2 0011: adc reference voltage comes from v ref 3 0100: adc reference voltage comes from v ref 4 1001: i nhibit to use 1010: adc reference voltage comes from v bg 2 1011: adc reference voltage comes from v bg 3 1100: adc reference voltage comes from v bg 4 other v alues: same as 0000 note: (1) when select v ref or v ref 2 or v ref 3 or v ref 4 as adc reference voltage, HT66F002/HT66F0025: pin share control bits (pas3, pas2) is (1, 0) to select vref as input. ht66f003: pin share control bits ( pas2, pas1 ) is (1, 0 ) to select vref as input. ht66f004: pin share control bits (pas3, pas2) is (1, 0) to select vref as input (2) v bg =1.04v (3) when savrs3=1, opa selects v bg as input. (4) if the programs select external reference volt age v ref and the internal reference voltage v bg as adc reference voltage, then the hardware will only choose the internal reference voltage v bg as an adc reference voltage input . a/d operation the st art bit is used to start and reset the a/d converter . when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the st art bit is brought from low to high but not low again, the adbz bit in the sadc0 register will be cleared to zero and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in process or not. when the a/d converter is reset by setting the st art bit from low to high, the adbz fag will be cleared to 0. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleare d to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program fow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle.
rev. 1.71 102 april 11, 2017 rev. 1.71 103 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom although the a/d clock source is determined by the system clock f sys , and by bits sack2~sack0, there a re so me l imitations o n t he m aximum a/ d c lock so urce sp eed t hat c an b e se lected. as t he recommended va lue of pe rmissible a/ d c lock pe riod, t adck , i s from 0.5 s t o 10 s, c are m ust be taken for system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the sack2~sack0 bits should not be set to 000b or 1 1xb. doing so will give a/d clock periods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d c lock period which may result in inaccurate a/d conversion values. controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he enadc bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the e nadc b it i s se t h igh t o p ower o n t he a/ d c onverter i nternal c ircuitry a c ertain d elay, a s indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by confguring the corresponding pin-shared control bits, if the enadc bit is high then some power will still be consumed. in power conscious applications it is therefore recom mended that the enadc is set low to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the internal adc power or from an external reference sources supplied on pin vref or v bg voltage. the desired selection is made u sing t he sa vrs 3~ sa vrs0 b its. as t he vr ef p in i s p in-shared wi th o ther f unctions, wh en t he vref pin is selected as the reference voltage supply pin, the vref pin-shared function control bits should be properly confgured to disable other pin functions. when v ref or v bg is selected by adc input or adc reference voltage, the opa needs to be enabled by setting enopa=1. reference savrs[ 3:0] description av dd 0000 adc reference voltage comes from av dd v ref 0001 adc reference voltage comes from external v ref v ref 2 0010 adc reference voltage comes from external v ref 2 v ref 3 0011 adc reference voltage comes from external v ref 3 v ref 4 0100 adc reference voltage comes from external v ref 4 v bg 2 1010 adc reference voltage comes from v bg 2 v bg 3 1011 adc reference voltage comes from v bg 3 v bg 4 1100 adc reference voltage comes from v bg 4 a/d converter reference voltage selection a/d converter input signal all of the a/d analog input pins are pin-shared with the i/o pins on port a and port b as well as other functions. the corredponding selection bits for each i/o pin in the p as r and pbs r registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other f unctions. i f t he p in-shared f unction c ontrol b its c onfgure i ts c orresponding p in a s a n a/ d analog channel input, the pin will be setup to be an a/d converter external channel input and the original pin functions dis abled. in this w ay, pins can be changed under program control to change their function between a /d inputs and other functions. a ll pull-high res istors, w hich are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac and pbc port control register to enable the a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the sa vrs[ 3 :0] in the sadc2 register. the analog input values must not be allowed to exceed the value of v ref.
rev. 1.71 102 april 11, 2017 rev. 1.71 103 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom conversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. t herefore a total of 16 a/ d clock cycles for an a/ d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 however, there is a usage limitation on the next a/d conversion after the current conversion is complete. when the current a /d convers ion is complete, the converted digital data w ill be s tored in the a/d data register pair and then latched after half an a/d clock cycle. if the st art bit is set to 1 i n h alf a n a/ d c lock c ycle a fter t he e nd o f a/ d c onversion, t he c onverted d igital d ata st ored in the a/d data register pair will be changed. therefore, it is recommended to initiate the next a/d conversion after a certain period greater than half an a/d clock cycle at t he e nd o f c urrent a /d conversion.
? ? ? ? ? ?? ? ? ? ? - ?? - ? ? ? ? ? a/d conversion timing
rev. 1.71 104 april 11, 2017 rev. 1.71 105 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion frequency by sacks2 ~ sacks 0 ? step 2 enable the adc by set enadc=1 ? step 3 select which pins will be confgure as adc analog inputs ? step 4 if input comes from i/o, set sains [2:0]=000 and then set sacs bit felds to corresponding p ad input if input comes from internal input, set sains[2:0] to corresponding internal input source ? step 5 select reference voltage comes from external v ref , av dd or v bg by savrs[3:0] note: (1) if select v ref as reference voltage, (pas3, pas2) = (1, 0) for HT66F002/ht66f004 (2) if select v ref as reference voltage, (pas2, pas1) = (1, 0) for ht66f003 ? step 6 select adc output data format by adrfs ? step 7 if adc interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bits, ade, must both set high in advance. ? step 8 the a/d convert procedure can now be initialized by set st art from low to high and then low again ? step 9 if adc is under conversion, adbz=1. after a/d conversion process is completed, the adbz fag will go low , and then output data can be read from s adoh and s adol registers. if the adc i nterrupt i s enabl ed and the st ack i s not ful l, dat a can be ac quired by int errupt servic e program. another way to get the a/d output data is polling the adbz fag.
rev. 1.71 104 april 11, 2017 rev. 1.71 105 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry c an b e swi tched o ff t o r educe p ower c onsumption, b y c learing t he e nadc b it i n t he sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device s contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= ( a v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value ( a v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.

? ? ? ? ? ? ?? ? ?
? ideal a/d transfer function
rev. 1.71 106 april 11, 2017 rev. 1.71 107 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom a/d programming example s the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the s adc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,0 b h mov s adc1,a ; select f sys /8 as a/d clock and switch off the bandgap reference voltage set enadc mov a, 03 h ; setup pasr to confgure pin an0 mov pasr ,a mov a, 20 h mov s adc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr s tart ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz adbz ; poll the s adc0 register adbz bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a, sado l ; read low byte conversion result value mov sado l_buffer,a ; save result to user defned register mov a, sado h ; read high byte conversion result value mov sado h_buffer,a ; save result to user defned register : : jmp st art_conversion ; start next a/d conversion
rev. 1.71 106 april 11, 2017 rev. 1.71 107 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,0 b h mov s adc1,a ; select f sys /8 as a/d clock and switch off the bandgap reference voltage set enadc mov a, 03 h ; setup pasr to confgure pin an0 mov pasr ,a mov a, 20 h mov s adc0,a ; enable and connect an0 channel to a/d converter start_conversion: clr s tart ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set e mi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; save acc to user defned memory mov a ,status mov s tatus_stack,a ; save status to user defned memory : : mov a, sado l ; read low byte conversion result value mov sadol _buffer,a ; save result to user defned register mov a, sado h ; read high byte conversion result value mov sadoh _buffer,a ; save result to user defned register : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a ,acc_stack ; restore acc from user defned memory reti
rev. 1.71 108 april 11, 2017 rev. 1.71 109 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device s contain several external interrupts and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 and int pin, while the internal interrupts are generated by various internal functions such as the tms, t ime base, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc 1 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi 1 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi int pin inte intf a/d converter ade adf multi-function mf0e mf0f time base tbne tbnf n=0 or 1 eeprom dee def tm stma0e stma0f stmp0e stmp0f interrupt register bit naming conventions C HT66F002/HT66F0025 function enable bit request flag notes global emi int pin inte intf a/d converter ade adf multi-function mfne mfnf n=0 or 1 time base tbne tbnf n=0 or 1 eeprom dee def tm stma0e stma0f stmp0e stmp0f ptma1e ptma1f ptmp1e ptmp1f interrupt register bit naming conventions C ht66f003
rev. 1.71 108 april 11, 2017 rev. 1.71 109 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom function enable bit request flag notes global emi intn pin intne intnf n=0 or 1 a/d converter ade adf multi-function mf0e mf0f time base tbne tbnf n=0 or 1 eeprom dee def tm ptmane ptmanf n=0 or 1 ptmpne ptmpnf interrupt register bit naming conventions C ht66f004 interrupt register contents ? HT66F002/HT66F0025 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int0s1 int0s0 intc0 tb1f tb0f intf tb1e tb0e inte emi intc1 adf def mf0f ade dee mf0e mfi0 stma0f stmp0f stma0e stmp0e ? ht66f003 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int0s1 int0s0 intc0 tb1f tb0f intf tb1e tb0e inte emi intc1 mf1f adf def mf0f mf1e ade dee mf0e mfi0 stma0f stmp0f stma0e stmp0e mfi1 ptma1f ptmp1f ptma1e ptmp1e ? ht66f004 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int1s1 int1s0 int0s1 int0s0 intc0 tb1f tb0f int0f tb1e tb0e int0e emi intc1 int1f adf def mf0f int1e ade dee mf0e mfi0 ptma1f ptmp1f ptma0f ptmp0f ptma1e ptmp1e ptma0e ptmp0e integ register C HT66F002/HT66F0025/ht66f003 bit 7 6 5 4 3 2 1 0 name int0s1 int0s0 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as "0" b it 1 ~ 0 int0s1, int0s0 : defnes int interrupt active edge 00 : disable interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt
rev. 1.71 110 april 11, 2017 rev. 1.71 111 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom integ register C ht66f004 bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as 0 bit 3 ~ 2 int1s1, int1s0 : defnes int1 interrupt active edge 00: disable interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt bit 1 ~ 0 int0s1, int0s0 : defnes int0 interrupt active edge 00: disable interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt intc0 register C HT66F002/HT66F0025/t66f003 bit 7 6 5 4 3 2 1 0 name tb1f tb0f intf tb1e tb0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 b it 7 unimplemented, read as "0" b it 6 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request b it 5 tb0f : time base 0 i nterrupt r equest flag 0: no request 1: interrupt request b it 4 intf : int i nterrupt r equest flag 0: no request 1: interrupt request b it 3 tb1e : time base 1 interrupt control 0: disable 1: enable b it 2 tb0 e : time base 0 i nterrupt control 0: disable 1: enable b it 1 int e : int i nterrupt control 0: disable 1: enable b it 0 emi : global i nterrupt control 0: disable 1: enable
rev. 1.71 110 april 11, 2017 rev. 1.71 111 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom intc0 register C ht66f004 bit 7 6 5 4 3 2 1 0 name tb1f tb0f int0f tb1e tb0e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tb1f : t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request flag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register C HT66F002/HT66F0025 bit 7 6 5 4 3 2 1 0 name adf def mf0f ade dee mf0e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 unimplemented, read as "0" b it 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request b it 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request b it 4 mf 0f : multi-function 0 interrupt request flag 0: no request 1: interrupt request b it 3 unimplemented, read as "0" b it 2 ad e : a/d converter interrupt control 0: disable 1: enable b it 1 de e : data eeprom interrupt control 0: disable 1: enable b it 0 mf0e : multi-function 0 interrupt control 0: disable 1: enable
rev. 1.71 112 april 11, 2017 rev. 1.71 113 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom intc1 register C ht66f003 bit 7 6 5 4 3 2 1 0 name mf1f adf def mf0f mf1e ade dee mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 mf 1f : multi-function 1 interrupt request flag 0: no request 1: interrupt request b it 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request b it 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request b it 4 mf 0f : multi-function 0 interrupt request flag 0: no request 1: interrupt request b it 3 mf 1e : multi-function 1 interrupt control 0: disable 1: enable b it 2 ad e : a/d converter interrupt control 0: disable 1: enable b it 1 de e : data eeprom interrupt control 0: disable 1: enable b it 0 mf0e : multi-function 0 interrupt control 0: disable 1: enable intc1 register C ht66f004 bit 7 6 5 4 3 2 1 0 name int1f adf def mf0f int1e ade dee mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int1f : int1 interrupt request flag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 mf0f : multi-function 0 interrupt request flag 0: no request 1: interrupt request bit 3 int1e : int1 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 mf0e : multi-function 0 interrupt control 0: disable 1: enable
rev. 1.71 112 april 11, 2017 rev. 1.71 113 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom mfi0 register C HT66F002 /HT66F0025/ht66f003 bit 7 6 5 4 3 2 1 0 name stma0f stmp0f stma0e stmp0e r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemented, read as "0" b it 5 stma0f : s tm comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 stmp0f : s tm comparator p match interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as "0" b it 1 s tma0e : s tm comparator a match interrupt control 0: disable 1: enable b it 0 s tmp0e : s tm comparator p match interrupt control 0: disable 1: enable mfi0 register C ht66f004 bit 7 6 5 4 3 2 1 0 name ptma1f ptmp1f ptma0f ptmp0f ptma1e ptmp1e ptma0e ptmp0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ptma1f : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 ptmp1f : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 ptma0f : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptmp0f : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ptma1e : tm1 comparator a match interrupt control 0: disable 1: enable bit 2 ptmp1e : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 ptma0e : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 ptmp0e : tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.71 114 april 11, 2017 rev. 1.71 115 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom mfi1 register C ht66f003 only bit 7 6 5 4 3 2 1 0 name ptma1f ptmp1f ptma1e ptmp1e r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemen ted, read as "0" b it 5 ptma1f : p tm comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 ptmp1f : p tm comparator p match interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as "0" b it 1 p tma1e : p tm comparator a match interrupt control 0: disable 1: enable b it 0 p tmp1e : p tm comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded.
rev. 1.71 114 april 11, 2017 rev. 1.71 115 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. all o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. int pin time base 0 intf tb0f inte tb0e emi 04h emi 08h eeprom def dee 0ch 10h 14h 18h 1ch interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high low m. funct. 1 mf1f mf1e interrupts contained within multi-function interrupts xxe enable bits xxf request flag, auto reset in isr legend xxf request flag, no auto reset in isr emi emi emi stm p stmp0f stmp0e stm a stma0f stma0e emi emi time base 1 tb1f tb1e m. funct. 0 mf0f mf0e a/d adf ade ptm p ptmp1f ptmp1e ptm a ptma1f ptma1e ht66f003 only interrupt name request flags enable bits interrupt structure C HT66F002/HT66F0025/ht66f003 int0 pin time base 0 int0f tb0f int0e tb0e emi 04h emi 08h eeprom def dee 0ch 10h 14h 18h 1ch interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high low int1 pin int1f int1e interrupts contained within multi-function interrupts xxe enable bits xxf request flag, auto reset in isr legend xxf request flag, no auto reset in isr emi emi emi ptm0 p ptmp0f ptmp0e ptm0 a ptma0f ptma0e emi emi time base 1 tb1f tb1e m. funct. 0 mf0f mf0e a/d adf ade ptm1 p ptmp1f ptmp1e ptm1 a ptma1f ptma1e interrupt name request flags enable bits interrupt structure C ht66f004
rev. 1.71 116 april 11, 2017 rev. 1.71 117 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom external interrupt the e xternal i nterrupt i s c ontrolled b y si gnal t ransitions o n t he p ins int a nd i nt0~int1. an external interrupt request will take place when the external interrupt request flag, intnf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external i nterrupt pi n. t o a llow t he progra m t o bra nch t o t he i nterrupt ve ctor a ddress, t he gl obal interrupt enable bit, emi, and the external interrupt enable bit, intne, must frst be set. additionally the correc t i nterrupt edge t ype must be se lected usi ng t he int eg regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i /o p ins, t hey c an o nly b e c onfigured a s e xternal i nterrupt p ins b y se tting t he p in-shared registers. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request flag, intnf , will be automatically reset and t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts. not e t hat t he pul l-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within t h ese de vice s t here a re up t o two mul ti-function i nterrupts. unl ike t he ot her i ndependent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf 0f~mf1f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupt s, will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the devices conta in an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termin ation of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the inte rrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converte r interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt flag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.71 116 april 11, 2017 rev. 1.71 117 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 b it 7 tbon : tb0 and tb1 control bit 0: disable 1: enable b it 6 tbck : select f tb clock 0: f tbc 1: f sys /4 b it 5 ~ 4 tb1 1 ~ tb10 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb b it 3 unimplemented, read as "0" b it 2 ~ 0 tb02 ~ tb00 : select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb

time base interrupt
rev. 1.71 118 april 11, 2017 rev. 1.71 119 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def , will also be automatically cleared. tm interrupt s the tms each has two interrupts. all of the tm interrupts are contain ed within the multi-function interrupts. for each of the tms there are two interrupt request flags xtmpnf and xtmanf and two enable bits xtmpne and xtmane. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit, mfnf , must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf1f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine.
rev. 1.71 118 april 11, 2017 rev. 1.71 119 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. scom function for lcd C ht66f004 the ht66f004 device has the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the i/o ports. the lcd signals are generated using the application program. lcd peration an external lcd panel can be driven using this device by confguring the i/o pins as common pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/of f function also controls the bias voltage setup function . this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the s comen bit in the s comc register is the overall mas ter control for the lcd driver . the lcd scomn pin is selected to be used for lcd driving by the corresponding pin-shared function selection bits. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
lcd com bias
rev. 1.71 120 april 11, 2017 rev. 1.71 121 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom lcd bias current control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd p anel whi ch a re b eing u sed. t he b ias re sistor c hoice i s i mplemented u sing t he ise l1 a nd isel0 bits in the scomc register. scomc bit 7 6 5 4 3 2 1 0 name isel1 isel0 scomen com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~5 isel1~isel0 : select resistor for r type lcd bias current(v dd =5v) 00: 2100 k (1/2 bias), i bias = 25a 01: 250 k (1/2 bias), i bias = 50a 10: 225 k (1/2 bias), i bias = 100a 11: 212.5 k (1/2 bias), i bias = 200a bit 4 scomen : lcd control bit 0: disable 1: enable when scomen is set, it will turn on the dc path of resistor to generate 1/2 v dd bias voltage. bit 3 com3en : pb3/an7 or scom3 selection 0: pb3/an7 1: scom3 bit 2 com2en : pb4/clo or scom2 selection 0: pb4/clo 1: scom2 bit 1 com1en : pc1 or scom1 selection 0: pc1 1: scom1 bit 0 com0en : pc0 or scom0 selection 0: pc0 1: scom0
rev. 1.71 120 april 11, 2017 rev. 1.71 121 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom application circuits vdd v dd res 10k ? ~ 100k ? 0.01f** 1n4148* vss 0.1f~1f 300 ? * 0.1f an0~an3 pa0~pa7 reset circuit HT66F002/HT66F0025 vdd v dd res 10k ? ~ 100k ? 0.01f** 1n4148* vss 0.1f~1f 300 ? * 0.1f an0~an3 pa0~pa7 reset circuit ht66f003 vdd v dd res 10k ? ~ 100k ? 0.01f** 1n4148* vss 0.1f~1f 300 ? * 0.1f reset circuit ht66f004 pb0~pb5 an0~an8 pa0~pa7 pb0~pb6 pc0~pc2 1rwh 5hfrpphqghg frpsrqhqw iru dgghg (6' surwhfwlrq 5hfrpphqghg frpsrqhqw lq hqylurqphqwv zkhuh srzhu olqh qrlvh lv vljql?fdqw
rev. 1.71 122 april 11, 2017 rev. 1.71 123 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.71 122 april 11, 2017 rev. 1.71 123 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.71 124 april 11, 2017 rev. 1.71 125 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] add data memory to acc 1 z, c, ac, ov addm a,[m] add acc to data memory 1 note z, c, ac, ov add a,x add immediate data to acc 1 z, c, ac, ov adc a,[m] add data memory to acc with carry 1 z, c, ac, ov adcm a,[m] add acc to data memory with carry 1 note z, c, ac, ov sub a,x subtract immediate data from the acc 1 z, c, ac, ov sub a,[m] subtract data memory from acc 1 z, c, ac, ov subm a,[m] subtract data memory from acc with result in data memory 1 note z, c, ac, ov sbc a,[m] subtract data memory from acc with carry 1 z, c, ac, ov sbcm a,[m] subtract data memory from acc with carry, result in data memory 1 note z, c, ac, ov daa [m] decimal adjust acc for addition with result in data memory 1 note c logic operation and a,[m] logical and data memory to acc 1 z or a,[m] logical or data memory to acc 1 z xor a,[m] logical xor data memory to acc 1 z andm a,[m] logical and acc to data memory 1 note z orm a,[m] logical or acc to data memory 1 note z xorm a,[m] logical xor acc to data memory 1 note z and a,x logical and immediate data to acc 1 z or a,x logical or immediate data to acc 1 z xor a,x logical xor immediate data to acc 1 z cpl [m] complement data memory 1 note z cpla [m] complement data memory with result in acc 1 z increment & decrement inca [m] increment data memory with result in acc 1 z inc [m] increment data memory 1 note z deca [m] decrement data memory with result in acc 1 z dec [m] decrement data memory 1 note z rotate rra [m] rotate data memory right with result in acc 1 none rr [m] rotate data memory right 1 note none rrca [m] rotate data memory right through carry with result in acc 1 c rrc [m] rotate data memory right through carry 1 note c rla [m] rotate data memory left with result in acc 1 none rl [m] rotate data memory left 1 note none rlca [m] rotate data memory left through carry with result in acc 1 c rlc [m] rotate data memory left through carry 1 note c
rev. 1.71 124 april 11, 2017 rev. 1.71 125 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom mnemonic description cycles flag affected data move mov a,[m] move data memory to acc 1 none mov [m],a move acc to data memory 1 note none mov a,x move immediate data to acc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch jmp addr jump unconditionally 2 none sz [m] skip if data memory is zero 1 note none sza [m] skip if data memory is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siza [m] skip if increment data memory is zero with result in acc 1 note none sdza [m] skip if decrement data memory is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a,x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read tabrd [m] read table (specifc page) to tblh and data memory 2 note none tabrdc [m] read table (current page) to tblh and data memory 2 note none tabrdl [m] read table (last page) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdog timer 1 to, pdf clr wdt1 pre-clear watchdog timer 1 to, pdf clr wdt2 pre-clear watchdog timer 1 to, pdf swap [m] swap nibbles of data memory 1 note none swapa [m] swap nibbles of data memory with result in acc 1 none halt enter power down mode 1 to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the t o and pdf flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.71 126 april 11, 2017 rev. 1.71 127 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.71 126 april 11, 2017 rev. 1.71 127 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.71 128 april 11, 2017 rev. 1.71 129 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.71 128 april 11, 2017 rev. 1.71 129 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.71 130 april 11, 2017 rev. 1.71 131 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.71 130 april 11, 2017 rev. 1.71 131 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.71 132 april 11, 2017 rev. 1.71 133 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.71 132 april 11, 2017 rev. 1.71 133 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.71 134 april 11, 2017 rev. 1.71 135 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.71 134 april 11, 2017 rev. 1.71 135 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.71 136 april 11, 2017 rev. 1.71 137 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.71 136 april 11, 2017 rev. 1.71 137 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 10-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.018 c 0.193 bsc d 0.069 e 0.039 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a f 6.00 bsc b 3.90 bsc c 0.30 0.45 c 4.90 bsc d 1.75 e 1.00 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.71 138 april 11, 2017 rev. 1.71 139 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 10-pin msop outline dimensions symbol dimensions in inch min. nom. max. a 0.043 a1 0.000 0.006 a2 0.030 0.033 0.037 b 0.007 0.013 c 0.003 0.009 d 0.118 bsc e 0.193 bsc e1 0.118 bsc e 0.020 bsc l 0.016 0.024 0.031 l1 0.037 bsc y 0.004 0 8 symbol dimensions in mm min. nom. max. a 1.10 a1 0.00 0.15 a2 0.75 0.85 0.95 b 0.17 0.33 c 0.08 0.23 d 3.0 bsc e 4.9 bsc e1 3.0 bsc e 0.5 bsc l 0.40 0.60 0.80 l1 0.95 bsc y 0.1 0 8
rev. 1.71 138 april 11, 2017 rev. 1.71 139 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 16-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.390 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.0 bsc b 3.9 bsc c 0.31 0.51 c 9.9 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.71 140 april 11, 2017 rev. 1.71 141 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 2 0-pin dip (300mil) outline dimensions fig 1. full lead packages fig 2. 1/2 lead p ackages see fig 1 symbol dimensions in inch min. nom. max. a 0.980 1.030 1.060 b 0.240 0.250 0.280 c 0. 115 0.130 0.195 d 0. 115 0.130 0.150 e 0.014 0.018 0.022 f 0.045 0.060 0.070 g 0.1bsc h 0.300 0.310 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.89 26.16 26.92 b 6.10 6.35 7.11 c 2.92 3.30 4.95 d 2.92 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.52 1.78 g 2.54 bsc h 7.62 7.87 8.26 i 10.92
rev. 1.71 140 april 11, 2017 rev. 1.71 141 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom see fig2 symbol dimensions in inch min. nom. max. a 0.945 0.965 0.985 b 0.275 0.285 0.295 c 0.120 0.135 0.150 d 0. 110 0.130 0.150 e 0.014 0.018 0.022 f 0.045 0.050 0.060 g 0.1bsc h 0.300 0.310 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.00 24.51 25.02 b 6.99 7.24 7.49 c 3.05 3.43 3.81 d 2.79 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.27 1.52 g 2.54 bsc h 7.62 7.87 8.26 i 10.92
rev. 1.71 142 april 11, 2017 rev. 1.71 143 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 20-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.406 bsc b 0.406 bsc c 0.012 0.020 c 0.504 bsc d 0.104 e 0.050 bsc f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7.50 bsc c 7.50 bsc c 12.80 bsc d 12.80 bsc e 1.27 bsc f 0.10 0.30 g 0.40 1.27 h 0.40 1.27 0 8
rev. 1.71 142 april 11, 2017 rev. 1.71 143 april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.155 bsc c 0.008 0.012 c 0.341 bsc d 0.069 e 0.025 bsc f 0.004 0.0098 g 0.016 0.05 h 0.004 0.01 0 D 8 symbol dimensions in mm min. nom. max. a 6.00 bsc b 3.90 bsc c 0.20 0.30 c 8.66 bsc d 1.75 e 0.635 bsc f 0.10 0.25 g 0.41 1.27 h 0.10 0.25 0 D 8
rev. 1.71 144 april 11, 2017 rev. 1.71 pb april 11, 2017 HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom HT66F002/HT66F0025/ht66f003/ht66f004 cost-effective a/d flash mcu with eeprom copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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